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Final Electrical Specifications
LTC1702 Dual 550kHz Synchronous 2-Phase Switching Regulator Controller
FEATURES
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DESCRIPTION
May 1999
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Two Independent Controllers in One Package Two Sides Run Out-of-Phase to Minimize CIN All N-Channel External MOSFET Architecture No External Current Sense Resistor Excellent Output Regulation: 1% Total Output Accuracy 550kHz Switching Frequency Minimizes External Component Size 1A to 25A Output Current per Channel High Efficiency over Wide Load Current Range Quiescent Current Drops Below 100A in Shutdown Small 24-Pin Narrow SSOP Package
APPLICATIONS
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Microprocessor Core and I/O Supplies Multiple Logic Supply Generator Distributed Power Applications High Efficiency Power Conversion
, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a trademark of Linear Technology Corporation.
The LTC(R)1702 is a dual switching regulator controller optimized for high efficiency with low input voltages. It includes two complete, on-chip, independent switching regulator controllers each designed to drive a pair of external N-channel MOSFET devices in a voltage mode feedback, synchronous buck configuration. The LTC1702 uses a constant-frequency, true PWM design switching at 550kHz, minimizing external component size and cost and maximing load transient performance. The synchronous buck architecture automatically shifts to discontinous and then to Burst ModeTM operation as the output load decreases, ensuring maximum efficiency over a wide range of load currents. The LTC1702 features an onboard reference trimmed to 0.5% and can provide better than 1% regulation at the converter outputs. Open-drain logic outputs indicate whether either output has risen to within 5% of the final output voltage and an optional latching FAULT mode protects the load if the output rises 15% above the intended voltage. Each channel can be enabled independently; with both channels disabled, the LTC1702 shuts down and supply current drops below 100A.
TYPICAL APPLICATION
DCP1 MBR0530T
28W Dual Output Power Supply
VIN, 5V
10 1F
DCP2 MBR0530T PVCC BOOST2 TG2 SW2 CCP2 1F
+
VCC BOOST1 TG1 SW1
VOUT1 1.8V 10A R11 10k 0.1%
LEXT1 1H 12A R31, 4.7k
Q11
CCP1 1F
RIMAX2, 47k Q22
Q21 C31 560pF RB1 7.96k 0.1%
D2 MBR330T RIMAX1, 22k
BG1 IMAX1 COMP1 FB1
LTC1702
BG2 IMAX2 COMP2 FB2
COUT1 470F x2
+
R21, 13k C11 330pF C21 680pF CSS1 0.1F
RUN/SS1 GND
RUN/SS2 PGND CSS2 0.1F LEXT1: MURATA LQT12535C1ROM12 LEXT2: COILTRONICS UP2B-2R2
CIN, COUT1, COUT2: KEMET T510X477M006AS
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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CIN 470F x2
LEXT2 Q12 2.2H 6A R32, 2.2k C32 820pF R12 4.99k 0.1% RB2 1.62k 0.1% R22, 20k C22 270pF
VOUT2 3.3V 3A
+
COUT2 470F
C12 120pF
1702 TA01
Q11, Q21: FAIRCHILD FDS6670A Q12, Q22: 1/2 SILICONIX Si9402
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LTC1702
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW PVCC BOOST1 BG1 TG1 SW1 IMAX1 PGOOD1 FCB RUN/SS1 1 2 3 4 5 6 7 8 9 24 IMAX2 23 BOOST2 22 BG2 21 TG2 20 SW2 19 PGND 18 PGOOD2 17 FAULT 16 RUN/SS2 15 COMP2 14 FB2 13 VCC
Supply Voltage VCC ........................................................................................... 7V BOOSTn ............................................................... 15V BOOSTn - SWn .................................................... 7V Input Voltage SWn ........................................................ - 1V to 15V All Other Inputs ......................... - 0.3V to VCC + 0.3V Peak Output Current < 10s TGn, BGn ............................................................... 5A Operating Temperature Range .................... 0C to 70C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1702CGN
COMP1 10 SGND 11 FB1 12
GN PACKAGE 24-LEAD NARROW PLASTIC SSOP
TJMAX = 125C, JA = 100C/ W
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VCC = 5V unless otherwise specified. (Note 3)
SYMBOL VCC PVCC BVCC ICC IPVCC IBOOST VFB VFB IFB VOUT VFCB VFCB IFCB VRUN ISS PARAMETER VCC Supply Voltage PVCC Supply Voltage BOOST Pin Voltage VCC Supply Current PVCC Supply Current BOOST Pin Current Feedback Voltage Feedback Voltage Line Regulation Feedback Current Output Voltage Load Regulation FCB Threshold FCB Feedback Hysteresis FCB Pin Current RUN/SS Pin RUN Threshold Soft Start Source Current RUN/SSn = 0V
q q
CONDITIONS
q
MIN 2.7 2.7 2.7
TYP
MAX 7 7 7
UNITS V V V mA A mA A mA A V %/V A % V mV A V A
Main Control Loop (Note 2) VBOOST - VSW (Note 2) Test Circuit 1 RUN/SS1 = RUN/SS2 = 0V (Note 5) Test Circuit 1 (Note 4) RUN/SS1 = RUN/SS2 = 0V (Note 5) Test Circuit 1 (Note 4) RUN/SS1 = RUN/SS2 = 0V Test Circuit 1 VCC = 2.7V to 7V (Note 6)
q q q q q q q q q q q q q
4.5 30 2.5 6 1.3 0.1 0.792 0.800 0.005 0.001 0.1 0.75 0.8 20 0.001 0.45 -2 0.55 -4
8 100 6 100 3 10 0.808 0.05 1 0.2 0.85 1 0.65 -6
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LTC1702
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VCC = 5V unless otherwise specified. (Note 3)
SYMBOL fOSC OSC2 DCMIN1 DCMIN2 DCMAX tNOV t r, tf AVFB GBW IERR VMIN VMAX AVILIM IIMAX Status Outputs VPGOOD VOLPG IPGOOD tPGOOD VFAULT VOLF IFAULT tFAULT PGOOD Trip Point PGOOD Output Low Voltage PGOOD Output Leakage PGOOD Delay Time FAULT Trip Point FAULT Output Low Voltage FAULT Output Current FAULT Delay Time VFB < VPGOOD to PGOOD VFB Relative to Regulated VOUT IFAULT = 1mA VFAULT = 0V VFB > VFAULT to FAULT
q q
PARAMETER Oscillator Frequency Converter 2 Oscillator Phase Minimum Duty Cycle Minimum Duty Cycle Maximum Duty Cycle Driver Nonoverlap Driver Rise/Fall Time FB DC Gain FB Gain Bandwidth FB Sink/Source Current MIN Comparator Threshold MAX Comparator Threshold ILIM Gain IMAX Source Current
CONDITIONS Test Circuit 1 Relative to Converter 1 VFB < VMAX VFB > VMAX Test Circuit 1 Test Circuit 1
q q q q q q
MIN 475 7 0 87
TYP 550 180 10 90 25 15
MAX 750
UNITS kHz DEG % %
Switching Characteristics
93 100 80
% ns ns dB MHz mA
Feedback Amplifier
q
74 3 815
85 25 10 760 840 40 785
q q q
mV mV dB
Current Limit Loop IMAX = 0V VFB Relative to Regulated VOUT PGOOD = 1mA
q
-7 - 10
-10 -5 0.03 0.1 100
-13 -3 0.1 1 + 20 0.1
A % V A s % V A s
q q q
+ 10
+ 15 0.03 - 10 25
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: PVCC and BVCC (VBOOST - VSW) must be greater than VGS(ON) of the external MOSFETs used to ensure proper operation. Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.
Note 4: Supply current in normal operation is dominated by the current needed to charge and discharge the external MOSFET gates. This current will vary with supply voltage and the external MOSFETs used. Note 5: Supply current in shutdown is dominated by external MOSFET leakage and may be significantly higher than the quiescent current drawn by the LTC1702, especially at elevated temperature. Note 6: This parameter is guaranteed by correlation and is not tested directly.
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LTC1702
PIN FUNCTIONS
PVCC (Pin 1): Driver Power Supply Input. PVCC provides power to the two BGn output drivers. PVCC must be connected to a voltage high enough to fully turn on the external MOSFETs Q21 and Q22. PVCC should generally be connected directly to VIN. PVCC requires at least a 1F bypass capacitor directly to PGND. BOOST1 (Pin 2): Controller 1 Top Gate Driver Supply. The BOOST1 pin supplies power to the floating TG1 driver. BOOST1 should be bypassed to SW1 with a 1F capacitor. An additional Schottky diode from VIN to BOOST1 pin will create a complete floating charge-pumped supply at BOOST1. No other external supplies are required. BG1 (Pin 3): Controller 1 Bottom Gate Drive. The BG1 pin drives the gate of the bottom N-channel synchronous switch MOSFET, Q21. BG1 is designed to drive up to 10,000pF of gate capacitance directly. If RUN/SS1 goes low, BG1 will go low, turning off Q21. If FAULT mode is tripped, BG1 will go high and stay high, keeping Q21 on until the power is cycled. TG1 (Pin 4): Controller 1 Top Gate Drive. The TG1 pin drives the gate of the top N-channel MOSFET, Q11. The TG1 driver draws power from the BOOST1 pin and returns to the SW1 pin, providing true floating drive to Q11. TG1 is designed to drive up to 10,000pF of gate capacitance directly. In shutdown or fault modes, TG1 will go low. SW1 (Pin 5): Controller 1 Switching Node. SW1 should be connected to the switching node of converter 1. The TG1 driver ground returns to SW1, providing floating gate drive to the top N-channel MOSFET switch, Q11. The voltage at SW1 is compared to IMAX1 by the current limit comparator while the bottom MOSFET, Q21, is on. IMAX1 (Pin 6): Controller 1 Current Limit Set. The IMAX1 pin sets the current limit comparator threshold for controller 1. If the voltage drop across the bottom MOSFET, Q21, exceeds the magnitude of the voltage at IMAX1, controller 1 will go into current limit. The IMAX1 pin has an internal 10A current source pull-up, allowing the current threshold to be set with a single external resistor to PGND. See the Current Limit Programming section for more information on choosing RIMAX. PGOOD1 (Pin 7): Controller 1 Power Good. PGOOD1 is an open-drain logic output. PGOOD1 will pull low whenever FB1 falls 5% below its programmed value. When RUN/SS1 is low (side 1 shut down), PGOOD1 will go high. FCB (Pin 8): Force Continuous Bar. The FCB pin forces both converters to maintain continuous synchronous operation regardless of load when the voltage at FCB drops below 0.8V. FCB is normally tied to VCC. To force continuous operation, tie FCB to SGND. FCB can also be connected to a feedback resistor divider from a secondary winding on one converter's inductor to generate a third regulated output voltage. Do not leave FCB floating. RUN/SS1 (Pin 9): Controller 1 Run/Soft Start. Pulling RUN/SS1 to SGND will disable controller 1 and turn off both of its external MOSFET switches. Pulling both RUN/SS pins down will shut down the entire LTC1702, dropping the quiescent supply current below 50A. A capacitor from RUN/SS1 to SGND will control the turn-on time and rate of rise of the controller 1 output voltage at power-up. An internal 4A current source pull-up at RUN/ SS1 pin sets the turn-on time at approximately 50ms/F. COMP1 (Pin 10): Controller 1 Loop Compensation. The COMP1 pin is connected directly to the output of the first controller's error amplifier and the input to the PWM comparator. An RC network is used at the COMP1 pin to compensate the feedback loop for optimum transient response. SGND (Pin 11): Signal Ground. All internal low power circuitry returns to the SGND pin. Connect to a low impedance ground, separated from the PGND node. All feedback, compensation and soft start connections should return to SGND. SGND and PGND should connect only at a single point, near the PGND pin and the negative plate of the CIN bypass capacitor. FB1 (Pin 12): Controller 1 Feedback Input. FB1 should be connected through a resistor network to VOUT1 to set the output voltage. The loop compensation network for controller 1 also connects to FB1. VCC (Pin 13): Power Supply Input. All internal circuits except the output drivers are powered from this pin. VCC should be connected to a low noise power supply voltage between 2.7V and 7V and should be bypassed to SGND with at least a 1F capacitor in close proximity to the LTC1702.
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LTC1702
PIN FUNCTIONS
FB2 (Pin 14): Controller 2 Feedback Input. See FB1. COMP2 (Pin 15): Controller 2 Loop Compensation. See COMP1. RUN/SS2 (Pin 16): Controller 2 Run/Soft Start. See RUN/ SS1. FAULT (Pin 17): Output Overvoltage Fault (Latched). The FAULT pin is an open-drain output with an internal 10A pull-up. If either regulated output voltage rises more than 15% above its programmed value for more than 25s, the FAULT output will go high and the entire LTC1702 will be disabled. When FAULT is high, both BG pins will go high, turning on the bottom MOSFET switches and pulling down the high output voltage. The LTC1702 will remain latched in this state until the power is cycled. When FAULT mode is active, the FAULT pin will be pulled up with an internal 10A current source. Tying FAULT directly to PGND will disable latched FAULT mode and will allow the LTC1702 to resume normal operation when the overvoltage fault is removed. PGOOD2 (Pin 18): Controller 2 Power Good. See PGOOD1. PGND (Pin 19): Power Ground. The BGn drivers return to this pin. Connect PGND to a high current ground node in close proximity to the sources of external MOSFETs, Q21 and Q22, and the VIN and VOUT bypass capacitors. SW2 (Pin 20): Controller 2 Switching Node. See SW1. TG2 (Pin 21): Controller 2 Top Gate Drive. See TG1. BG2 (Pin 22): Controller 2 Bottom Gate Drive. See BG1. BOOST2 (Pin 23): Controller 2 Top Gate Driver Supply. See BOOST1. IMAX2 (Pin 24): Controller 2 Current Limit Set. See IMAX1.
BLOCK DIAGRAM
VCC
OSC 550kHz DIS 4A RUN/SS1,2 COMP1,2 SOFT START 100s DELAY 25s DELAY 10A IMAX1,2 800mV 775mV 825mV 920mV ILIM + FB - MIN MAX FLT FROM OTHER CONTROLLER
500mV
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FCB BURST LOGIC
PVCC BOOST1,2 TG1,2 DRIVE LOGIC SW1,2 BG1,2
90% DUTY CYCLE
PGND SGND
PGOOD1,2
FAULT
FB1,2
SHUTDOWN TO THIS CONTROLLER
1702 BD
SHUTDOWN TO ENTIRE CHIP
FROM OTHER CONTROLLER
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LTC1702
TEST CIRCUIT
Test Circuit 1
5V
0.1F
IBOOST1 BOOST1
ICC VCC
IPVCC PVCC BOOST2 TG2 BG2 SW2 IMAX2
IBOOST2
+
100F
fOSC MEASURED
TG1 5V 2000pF 2000pF BG1 SW1 10k IMAX1 FCB LTC1702 PGOOD1
2000pF
2000pF 5V 10k
VPGOOD1
PGOOD2 FAULT
VPGOOD2 VFAULT 2k VFB2
2k VFB1
RUN/SS1 COMP1 FB1 GND
RUN/SS2 COMP2 FB2 PGND
1702 TC
APPLICATIONS INFORMATION
OVERVIEW The LTC1702 is a dual, step-down (buck), voltage mode feedback switching regulator controller. It is designed to be used in a synchronous switching architecture with two external N-channel MOSFETs per channel. It is intended to operate from a low voltage input supply (7V maximum) and provide a high power, high efficiency, precisely regulated output voltage. Several features make it particularly suited for microprocessor supply regulation. Output regulation is extremely tight, with DC line and load regulation and initial accuracy better than 1%, and total regulation including transient response inside of 3% with a properly designed circuit. The 550kHz switching frequency allows the use of physically small, low value external components without compromising performance. The LTC1702's internal feedback amplifier is a 25MHz gain-bandwidth op amp, allowing the use of complex multipole/zero compensation networks. This allows the feedback loop to maintain acceptable phase margin at higher frequencies than traditional switching regulator controllers allow, improving stability and maximizing transient response. The 800mV internal reference allows regulated output voltages as low as 800mV without external level shifting amplifiers. The LTC1702's synchronous switching logic transitions automatically into Burst Mode operation, maximizing efficiency with light loads. Onboard power-good and overvoltage (OV) fault flags indicate when the output is in regulation or an OV fault has occurred. The OV flag can be set to latch the device off when an OV fault has occurred, or to automatically resume operation when the fault is removed. The LTC1702 takes a low input voltage and generates two lower output voltages at very high currents. Its strengths are small size, unmatched regulation and transient response and high efficiency. This combination makes it ideal for providing multiple low voltage logic supplies to microprocessors or high density ASICs in systems using a "2-step" regulation architecture, used in portable and advanced desktop computers.
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LTC1702
APPLICATIONS INFORMATION
2-Step Conversion "2-step" architectures use a primary regulator to convert the input power source (batteries or AC line voltage) to an intermediate supply voltage, often 5V. This intermediate voltage is then converted to the low voltage, high current supplies required by the system using a secondary regulator-- the LTC1702. 2-step conversion eliminates the need for a single converter that converts a high input voltage to a very low output voltage, often an awkward design challenge. It also fits naturally into systems that continue to use the 5V supply to power portions of their circuitry, or have excess 5V capacity available as newer circuit designs shift the current load to lower voltage supplies. Each regulator in a typical 2-step system maintains a relatively low step-down ratio (5:1 or less), running at high efficiency while maintaining a reasonable duty cycle. In contrast, a regulator taking a single step from a high input voltage to a 1.xV or 2.xV output must run at a very narrow duty cycle, mandating trade-offs in external component values and compromising efficiency and transient response. The efficiency loss can exceed that of using a 2-step solution (see the 2-Step Efficiency Calculation section and Figure 10). Further complicating the calculation is the fact that many systems draw a significant fraction of their total power off the intermediate 5V supply, bypassing the low voltage supply. 2-step solutions using the LTC1702 usually match or exceed the total system efficiency of single-step solutions, and provide the additional benefits of improved transient response, reduced PCB area and simplified power trace routing. 2-step regulation can buy advantages in thermal management as well. Power dissipation in the LTC1702 portion of a 2-step circuit is lower than it would be in a typical 1-step converter, even in cases where the 1-step converter has higher total efficiency than the 2-step system. In a typical microprocessor core supply regulator, for example, the regulator is usually located right next to the CPU. In a 1-step design, all of the power dissipated by the core regulator is right there next to the hot CPU, aggravating thermal management. In a 2-step LTC1702 design, a significant percentage of the power lost in the core regulation system happens in the 5V supply, which is usually located away from the CPU. The power lost to heat in the LTC1702 section of the system is relatively low, minimizing the added heat near the CPU. See the Optimizing Performance section for a detailed explanation of how to calculate system efficiency. 2-Phase Operation The LTC1702 dual switching regulator controller also features the considerable benefits of 2-phase operation. Notebook computers, hand-held terminals and automotive electronics all benefit from the lower input filtering requirement, reduced electromagnetic interference (EMI) and increased efficiency associated with 2-phase operation. Why the need for 2-phase operation? Up until the LTC1702, constant-frequency dual switching regulators operated both channels in phase (i.e., single-phase operation). This means that both topside MOSFETs turned on at the same time, causing current pulses of up to twice the amplitude of those for one regulator to be drawn from the input capacitor. These large amplitude current pulses increased the total RMS current flowing from the input capacitor, requiring the use of more expensive input capacitors and increasing both EMI and losses in the input capacitor and input power supply. With 2-phase operation, the two channels of the LTC1702 are operated 180 degrees out of phase. This effectively interleaves the current pulses coming from the switches, greatly reducing the overlap time where they add together. The result is a significant reduction in total RMS input current, which in turn allows less expensive input capacitors to be used, reduces shielding requirements for EMI and improves real world operating efficiency. Figure 7 shows example waveforms for a single switching regulator channel versus a 2-phase LTC1702 system with both sides switching. A single-phase dual regulator with both sides operating would exhibit double the single side numbers. In this example, 2-phase operation reduced the RMS input current from 9.3ARMS (2 x 4.66ARMS) to 4.8ARMS. While this is an impressive reduction in itself, remember that the power losses are proportional to IRMS2, meaning that the actual power wasted is reduced by a
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LTC1702
APPLICATIONS INFORMATION
factor of 3.75. The reduced input ripple voltage also means less power is lost in the input power path, which could include batteries, switches, trace/connector resistances and protection circuitry. Improvements in both conducted and radiated EMI also directly accrue as a result of the reduced RMS input current and voltage. Small Footprint The LTC1702 operates at a 550kHz switching frequency, allowing it to use low value inductors without generating excessive ripple currents. Because the inductor stores less energy per cycle, the physical size of the inductor can be reduced without risking core saturation, saving PCB board space. The high operating frequency also means less energy is stored in the output capacitors between cycles, minimizing their required value and size. The remaining components, including the 150mil SSOP-24 LTC1702, are tiny, allowing an entire dual-output LTC1702 circuit to be constructed in 1.5in2 of PCB space. Further, this space is generally located right next to the microprocessor or in some similarly congested area, where PCB real estate is at a premium. The fact that the LTC1702 runs off the 5V supply, often available from a power plane, is an added benefit in portable systems --it does not require a dedicated supply line running from the battery. Fast Transient Response The LTC1702 uses a fast 25MHz GBW op amp as an error amplifier. This allows the compensation network to be designed with several poles and zeros in a more flexible configuration than with a typical gm feedback amplifier. The high bandwidth of the amplifier, coupled with the high switching frequency and the low values of the external inductor and output capacitor, allow very high loop crossover frequencies. The low inductor value is the other half of the equation--with a typical value on the order of 1H, the inductor allows very fast di/dt slew rates. The result is superior transient response compared with conventional solutions. High Efficiency The LTC1702 uses a synchronous step-down (buck) architecture, with two external N-channel MOSFETs per output. A floating topside driver and a simple external charge pump provide full gate drive to the upper MOSFET. The voltage mode feedback loop and MOSFET VDS current limit sensing remove the need for an external current sense resistor, eliminating an external component and a source of power loss in the high current path. Properly designed circuits using low gate charge MOSFETs are capable of efficiencies exceeding 90% over a wide range of output voltages. ARCHITECTURE DETAILS The LTC1702 dual switching regulator controller includes two identical, independent regulator channels. The two sides of the chip and their corresponding external components act independently of each other with the exception of the common input bypass capacitor and the FCB and FAULT pins, which affect both channels. In the following discussions, when a pin is referred to without mentioning which side is involved, that discussion applies equally to both sides. Switching Architecture Each half of the LTC1702 is designed to operate as a synchronous buck converter (Figure 1). Each channel includes two high power MOSFET gate drivers to control external N-channel MOSFETs Q1 and Q2. These drivers have 0.5 output impedances and can carry well over an amp of continuous current with peak currents up to 5A to slew large MOSFET gates quickly. The external MOSFETs are connected with the drain of Q1 attached to the input supply and the source of Q1 at the switching node SW. Q2 is the synchronous rectifier with its drain at SW and its source at PGND. SW is connected to one end of the inductor, with the other end connected to VOUT. The output capacitor is connected from VOUT to PGND.
VIN
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CIN TG LTC1702 SW PGND BG Q2 Q1 LEXT VOUT COUT
1702 F01
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Figure 1. Synchronous Buck Architecture
LTC1702
APPLICATIONS INFORMATION
When a switching cycle begins, Q2 is turned off and Q1 is turned on. SW rises almost immediately to VIN and the inductor current begins to increase. When the PWM pulse finishes, Q1 turns off and one nonoverlap interval later, Q2 turns on. Now SW drops to PGND and the inductor current decreases. The cycle repeats with the next tick of the master clock. The percentage of time spent in each mode is controlled by the duty cycle of the PWM signal, which in turn is controlled by the feedback amplifier. The master clock runs at a 550kHz rate and turns Q1 once every 1.8s. In a typical application with a 5V input and a 1.6V output, the duty cycle will be set at 1.6/5 x 100% or 32% by the feedback loop. This will give roughly a 575ns on-time for Q1 and a 1.22s on-time for Q2. This constant frequency operation brings with it a couple of benefits. Inductor and capacitor values can be chosen with a precise operating frequency in mind and the feedback loop components can be similarly tightly specified. Noise generated by the circuit will always be in a known frequency band with the 550kHz frequency designed to leave the 455kHz IF band free of interference. Subharmonic oscillation and slope compensation, common headaches with constant frequency current mode switchers, are absent in voltage mode designs like the LTC1702. During the time that Q1 is on, its source (the SW pin) is at VIN. VIN is also the power supply for the LTC1702. However, Q1 requires VIN + VGS(ON) at its gate to achieve minimum RON. This presents a problem for the LTC1702-- it needs to generate a gate drive signal at TG higher than its highest supply voltage. To get around this, the TG driver runs from floating supplies, with its negative supply attached to SW and its power supply at BOOST. This allows it to slew up and down with the source of Q1. In combination with a simple external charge pump (Figure 2), this allows the LTC1702 to completely enhance the gate of Q1 without requiring an additional, higher supply voltage. The two channels of the LTC1702 run from a common clock, with the phasing chosen to be 180 from side 1 to side 2. This has the effect of doubling the frequency of the switching pulses seen by the input bypass capacitor, significantly lowering the RMS current seen by the capacitor and reducing the value required (see the 2-Phase section).
PVCC BOOST TG SW BG LTC1702 PGND DCP CCP 1F
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VIN
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CIN
Q1
LEXT VOUT
+
Q2 COUT
1702 F02
Figure 2. Floating TG Driver Supply
Feedback Amplifier Each side of the LTC1702 senses the output voltage at VOUT with an internal feedback op amp (see Block Diagram). This is a real op amp with a low impedance output, 85dB open-loop gain and 25MHz gain-bandwidth product. The positive input is connected internally to an 800mV reference, while the negative input is connected to the FB pin. The output is connected to COMP, which is in turn connected to the soft start circuitry and from there to the PWM generator. Unlike many regulators that use a resistor divider connected to a high impedance feedback input, the LTC1702 is designed to use an inverting summing amplifier topology with the FB pin configured as a virtual ground. This allows flexibility in choosing pole and zero locations not available with simple gm configurations. In particular, it allows the use of "type 3" compensation, which provides a phase boost at the LC pole frequency and significantly improves loop phase margin (see Figure 3). Appendix A contains a detailed explanation of type 3 feedback loops.
+
COMP FB
0.8V FB
R3 R1
C3
-
C2 C1
VOUT RB
R2
1702 F03
Figure 3. "Type 3" Feedback Loop
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LTC1702
APPLICATIONS INFORMATION
MIN/MAX Two additional feedback loops keep an eye on the primary feedback amplifier and step in if the feedback node moves 5% from its nominal 800mV value. The MAX comparator (see Block Diagram) activates whenever FB rises more than 5% above 800mV. It immediately turns the top MOSFET (Q1) off and the bottom MOSFET (Q2) on and keeps them that way until FB falls back within 5%. This pulls the output down as fast as possible, preventing damage to the (often expensive) load. If FB rises because the output is shorted to a higher supply, Q2 will stay on until the short goes away, the higher supply current limits or Q2 dies trying to save the load. This behavior provides maximum protection against overvoltage faults at the output, while allowing the circuit to resume normal operation when the fault is removed. The overvoltage protection circuit can optionally be set to latch the output off permanently (see the Overvoltage Fault section). The MIN comparator (see Block Diagram) trips whenever FB is more than 5% below 800mV and immediately forces the switch duty cycle to 90% to bring the output voltage back into range. It releases when FB is within the 5% window. MIN is disabled when the soft start or current limit circuits are active--the only two times that the output should legitimately be below its regulated value. Notice that the FB pin is the virtual ground node of the feedback amplifier. A typical compensation network does not include local DC feedback around the amplifier, so that the DC level at FB will be an accurate replica of the output voltage, divided down by R1 and RB (Figure 3). However, the compensation capacitors will tend to attenuate AC signals at FB, especially with low bandwidth type 1 feedback loops. This creates a situation where the MIN and MAX comparators do not respond immediately to shifts in the output voltage, since they monitor the output at FB. Maximizing feedback loop bandwidth will minimize these delays and allow MIN and MAX to operate properly. See the Feedback Loop/Compensation section. PGOOD Flags The MIN comparator performs another function; it drives the external "power good" pin (PGOOD) through a 100s delay stage. PGOOD is an open-drain output, allowing it to be wire-OR'ed with other open-drain/open-collector signals. An external pull-up resistor is required for PGOOD to swing high. Any time the FB pin is more than 5% below the programmed value for more than 100s, PGOOD will pull low, indicating that the output is out of regulation. PGOOD remains active during soft start and current limit, even though the MIN comparator has no effect on the duty cycle during these times. The 100s delay ensures that short output transient glitches that are successfully "caught" by the MIN comparator don't cause momentary glitches at the PGOOD pin. Note that the PGOOD pin only watches MIN, not MAX--it does not indicate if the output is 5% above the programmed value. When either side of the LTC1702 is in shutdown, its associated PGOOD pin will go high. This behavior allows a valid PGOOD reading when the two PGOOD pins are tied together, even if one side is shut down. It also reduces quiescent current by eliminating the excess current drawn by the pull-up at the PGOOD pin. As soon as the RUN/SS pin rises above the shutdown threshold and the side comes out of shutdown, the PGOOD pin will pull low until the output voltage is valid. If both sides are shut down at the same time, both PGOOD pins will go high. To avoid confusion, if either side of the LTC1702 is shut down, the host system should ignore the associated PGOOD pin. SHUTDOWN/SOFT START Each half of the LTC1702 has a RUN/SS pin. The RUN/SS pins perform two functions: when pulled to ground, each shuts down its half of the LTC1702, and each acts as a conventional soft start pin, enforcing a maximum duty cycle limit proportional to the voltage at RUN/SS. An internal 4A current source pull-up is connected to each RUN/SS pin, allowing a soft start ramp to be generated with a single external capacitor to ground. The 4A current sources are active even when the LTC1702 is shut down, ensuring the device will start when any external pull-down at RUN/SS is released. Either side can be shut down without affecting the operation of the other side. If both sides are shut down at the same time, the LTC1702 goes into a micropower sleep mode, and quiescent current drops below 50A. Entering sleep mode also resets the FAULT latch, if it was set.
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LTC1702
APPLICATIONS INFORMATION
Each RUN/SS pin shuts down its half of the LTC1702 when it falls below about 0.5V. Between 0.5V and about 1V, that half is active, but the maximum duty cycle is limited to 10%. The maximum duty cycle limit increases linearly between 1V and 2.5V, reaching its final value of 90% when RUN/SS is above 2.5V. Somewhere before this point, the feedback amplifier will assume control of the loop and the output will come into regulation. When RUN/SS rises to 0.5V below VCC, the MIN feedback comparator is enabled, and the LTC1702 is in full operation (see Figure 4). CURRENT LIMIT The LTC1702 includes an onboard current limit circuit that limits the maximum output current to a user-programmed level. It works by sensing the voltage drop across Q2 during the time that Q2 is on and comparing that voltage to a user-programmed voltage at IMAX. Since Q2 looks like a low value resistor during its on-time, the voltage drop across it is proportional to the current flowing in it. In a buck converter, the average current in the inductor is equal to the output current. This current also flows through Q2 during its on-time. Thus, by watching the voltage across Q2, the LTC1702 can monitor the output current. Any time Q2 is on and the current flowing to the output is reasonably large, the SW node at the drain of Q2 will be somewhat negative with respect to PGND. The LTC1702 senses this voltage and inverts it to allow it to compare the sensed voltage with a positive voltage at the IMAX pin. The IMAX pin includes a trimmed 10A pull-up, enabling the user to set the voltage at IMAX with a single resistor, RIMAX, to ground. The LTC1702 compares the two inputs and begins limiting the output current when the magnitude of the negative voltage at the SW pin is greater than the voltage at IMAX. The current limit detector is connected to an internal gm amplifier that pulls a current from the RUN/SS pin proportional to the difference in voltage magnitudes between the SW and IMAX pins. This current begins to discharge the soft start capacitor at RUN/SS, reducing the duty cycle and controlling the output voltage until the current drops below the limit. The soft start capacitor needs to move a fair amount before it has any effect on the duty cycle, adding a delay until the current limit takes effect (Figure 4). This allows the LTC1702 to experience brief overload conditions without affecting the output voltage regulation. The delay also acts as a pole in the current limit loop to
VOUT 0V
5V 4.5V
VRUN/SS
2.5V
1.0V 0.5V 0V LTC1702 ENABLED RUN/SS CONTROLS DUTY CYCLE COMP CONTROLS DUTY CYCLE MIN COMPARATOR ENABLED RUN/SS CONTROLS DUTY CYCLE
START-UP
Figure 4. Soft Start Operation in Start-Up and Current Limit
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2.5V
NORMAL OPERATION
CURRENT LIMIT
1702 F04
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LTC1702
APPLICATIONS INFORMATION
enhance loop stability. Larger overloads cause the soft start capacitor to pull down quickly, protecting the output components from damage. The current limit gm amplifier includes a clamp to prevent it from pulling RUN/SS below 0.5V and shutting off the device. Power MOSFET RDS(ON) varies from MOSFET to MOSFET, limiting the accuracy obtainable from the LTC1702 current limit loop. Additionally, ringing on the SW node due to parasitics can add to the apparent current, causing the loop to engage early. The LTC1702 current limit is designed primarily as a disaster prevention, "no blow up" circuit, and is not useful as a precision current regulator. It should typically be set around 50% above the maximum expected normal output current to prevent component tolerances from encroaching on the normal current range. See the Current Limit Programming section for advice on choosing a valve for RIMAX. DISCONTINUOUS/Burst Mode OPERATION Theory of operation The LTC1702 switching logic has three modes of operation. Under heavy loads, it operates as a fully synchronous, continuous conduction switching regulator. In this mode of operation ("continuous" mode), the current in the inductor flows in the positive direction (toward the output) during the entire switching cycle, constantly supplying current to the load. In this mode, the synchronous switch (Q2) is on whenever Q1 is off, so the current always flows through a low impedance switch, minimizing voltage drop and power loss. This is the most efficient mode of operation at heavy loads, where the resistive losses in the power devices are the dominant loss term. Continuous mode works efficiently when the load current is greater than half of the ripple current in the inductor. In a buck converter like the LTC1702, the average current in the inductor (averaged over one switching cycle) is equal to the load current. The ripple current is the difference between the maximum and the minimum current during a switching cycle (see Figure 5a). The ripple current depends on inductor value, clock frequency and output voltage, but is constant regardless of load as long as the LTC1702 remains in continuous mode. See the Inductor Selection section for a detailed description of ripple current. As the output load current decreases in continuous mode, the average current in the inductor will reach a point where it drops below half the ripple current. At this point, the current in the inductor will reverse during a portion of the switching cycle, or begin to flow from the output back to the input. This does not adversely affect regulation, but does cause additional losses as a portion of the inductor current flows back and forth through the resistive power switches, giving away a little more power each time and lowering the efficiency. There are some benefits to allowing this reverse current flow: the circuit will maintain regulation even if the load current drops below zero (the load supplies current to the LTC1702) and the output ripple voltage and frequency remain constant at all loads, easing filtering requirements. Circuits that take advantage of this behavior can force the LTC1702 to operate in continuous mode at all loads by tying the FCB (Force Continuous Bar) pin to ground. Discontinuous Mode To minimize the efficiency loss due to reverse current flow at light loads, the LTC1702 switches to a second mode of operation: discontinuous mode (Figure 5b). In discontinuous mode, the LTC1702 detects when the inductor current approaches zero and turns off Q2 for the remainder of the switch cycle. During this time, the voltage at the SW pin will float about VOUT, the voltage across the inductor will be zero, and the inductor current remains zero until the next switching cycle begins and Q1 turns on again. This prevents current from flowing backwards in Q2, eliminating that power loss term. It also reduces the ripple current in the inductor as the output current approaches zero. The LTC1702 detects that the inductor current has reached zero by monitoring the voltage at the SW pin while Q2 is on. Since Q2 acts like a resistor, SW should ideally be right at 0V when the inductor current reaches zero. In reality, the SW node will ring to some degree immediately after it is switched to ground by Q2, causing some uncertainty as to the actual moment the average current in Q2 goes to zero. The LTC1702 minimizes this effect by ignoring the SW node for a fixed 50ns after Q2 turns on when the ringing is
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LTC1702
APPLICATIONS INFORMATION
IRIPPLE
DISCONTINUOUS COMPARATOR TURNS OFF BG 0V TIME 50ns BLANK TIME
1702 F05a
INDUCTOR CURRENT
IAVERAGE
TIME
Figure 5a. Continuous Mode
INDUCTOR CURRENT
IRIPPLE
IAVERAGE TIME
1702 F05b
Figure 5b. Discontinuous Mode
most severe, and by including a few millivolts offset in the comparator that monitors the SW node. Despite these precautions, some combinations of inductor and layout parasitics can cause the LTC1702 to enter discontinuous mode erratically. In many cases, the time that Q2 turns off will correspond to a peak in the ringing waveform at the SW pin (Figure 6). This erratic operation isn't pretty, but retains much of the efficiency benefit of discontinuous mode and maintains regulation at all times. Burst Mode Operation Discontinuous mode removes a loss term due to resistive drop in Q2, but the LTC1702 is still switching Q1 and Q2 on and off once a cycle. Each time an external MOSFET is turned on, the internal driver must charge its gate to VCC. Each time it is turned off, that charge is lost to ground. At the high switching frequencies that the LTC1702 operates at, the charge lost to the gates can add up to tens of milliamps from VCC. As the load current continues to drop, this quickly become the dominant power loss term, reducing efficiency once again. Once again, the LTC1702 switches to a new mode to minimize efficiency loss: Burst Mode operation. As the
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VSW
5V
VBG
0V TIME
1702 F06
Figure 6. Ringing at SW Causes Discontinuous Comparator to Trip Early
circuit goes deeper and deeper into discontinuous mode, the total time Q1 and Q2 are on reduces. However, the ratio of the time that Q1 is on to the time that Q2 is on must remain constant for the output to stay in regulation. An internal timer circuit forces Q1 to stay on for at least 10% of a normal switching cycle. When the load drops to the point that the output requires less than 10% on-time at Q1, the output voltage will begin to rise. The LTC1702 senses this rise and shuts both Q1 and Q2 off completely, skipping several switching cycles until the output falls back into range. It then resumes switching in discontinuous mode with Q1 at 10% duty cycle and the burst sequence repeats. The total deviation from the regulated output is within the 1% regulation tolerance of the LTC1702. In Burst Mode operation, both resistive loss and switching loss are minimized while keeping the output in regulation. The ripple current will be set by the 10% Q1 on-time and the input supply voltage and is the lowest of all three operating modes. As the load current falls to zero in Burst Mode operation, the most significant loss term becomes the 3mA quiescent current drawn by each side of the LTC1702--usually much less than the minimum load current in a typical low voltage logic system. Burst Mode operation maximizes efficiency at low load currents, but can cause low frequency ripple in the output voltage as the cycle-skipping circuitry switches on and off. FCB Pin In some circumstances, it is desirable to control or disable discontinuous and Burst Mode operations. The FCB (Force
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LTC1702
APPLICATIONS INFORMATION
Continuous Bar) pin allows the user to do this. When the FCB pin is high, the LTC1702 is allowed to enter discontinuous and Burst Mode operations at either side as required. If FCB is taken low, discontinuous and Burst Mode operations are disabled and both sides of the LTC1702 run in continuous mode regardless of load. This does not affect output regulation but does reduce efficiency at low output currents. The FCB pin threshold is specified at 0.8V 10mV, and includes 10mV of hysteresis, allowing it to be used as a precision small-signal comparator. Paralleling Outputs Synchronous regulators (like the LTC1702) are known for their bullheadedness when their outputs are paralleled with other regulators. In particular, a synchronous regulator paralleled with another regulator whose output is slightly higher (perhaps just by millivolts) will happily sink amps of current attempting to pull its own output back down to what it thinks is the right value. The LTC1702 discontinuous mode allows it to be paralleled with another regulator without fighting. A typical system might use the LTC1702 as a primary regulator and a small LDO as a backup regulator to keep SRAM alive when the main power is off. When the LTC1702 is shut down (by pulling RUN/SS to ground), both Q1 and Q2 turn off and the output goes into a high impedance state, allowing the smaller regulator to support the output voltage. However, if the LTC1702 is powered back up in continuous mode, it will begin a soft start cycle with a low duty cycle, pulling the output down and corrupting the data stored in SRAM. The solution is to tie FCB high, allowing the device to start in discontinuous mode. Any reverse current flow in Q2 will trip the discontinuous mode circuitry, preventing the LTC1702 from pulling down the output. OVERVOLTAGE FAULT The LTC1702 includes a single overvoltage fault flag for both channels: FAULT. FAULT is an open-drain output with an internal 10A pull-up. If either FB pin rises more than 15% above the nominal 800mV value for more than 25s, the overvoltage comparator will trip, setting an internal latch. This latch releases the pull-down at FAULT, allowing the 10A pull-up to take it high. When FAULT goes high, the LTC1702 stops all switching, turns both Q2 (bottom synchronous) MOSFETs on continuously and remains in this state until both RUN/SS pins are pulled low simultaneously, the power supply is recycled, or the FAULT pin is pulled low externally. This behavior is intended to protect a potentially expensive load from overvoltage damage at all costs. Under some conditions, this behavior can cause the output voltage to undershoot below ground. If latched FAULT mode is used, a Schottky diode should be added with its cathode at the output and its anode at ground to clamp the negative voltage to a safe level and prevent possible damage to the load and the output capacitors. Note that in overvoltage conditions, the MAX comparator will kick in at just +5%, turning M2 on continuously long before the output reaches +15%. Under most fault conditions, this is adequate to bring the output back down without firing the fault latch. Additionally, if MAX successfully keeps the output below +15%, the LTC1702 will resume normal regulation as soon as the output overvoltage fault is resolved. In some circuits, the OV latch can be a liability. Consider a circuit where the output voltage at one channel may be changed on the fly by switching in different feedback resistors. A downward adjustment of greater than 15% will fire the fault latch, disabling both sides of the LTC1702 until the power is recycled. In circuits such as this, the fault latch can be disabled by grounding the FAULT pin. The internal latch will still be set the first time the output exceeds +15%, but the 10A current source pull-up will not be able to pull FAULT high, and the LTC1702 will ignore the latch and continue normal operation. The MAX comparator will act as usual, turning on Q2 until output is within range and then allowing the loop to resume normal operation. FAULT can also be pulled down with external open-collector logic to restart a fault-latched LTC1702 as an alternative to recycling the power. Note that this will not reset the internal latch; if the external pull-down is released, the LTC1702 will reenter FAULT mode. To reset the latch, pull both RUN/SS pins low simultaneously or cycle the power.
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LTC1702
APPLICATIONS INFORMATION
EXTERNAL COMPONENT SELECTION POWER MOSFETs Getting peak efficiency out of the LTC1702 depends strongly on the external MOSFETs used. The LTC1702 requires at least two external MOSFETs per side--more if one or more of the MOSFETs are paralleled to lower on-resistance. To work efficiently, these MOSFETs must exhibit low RDS(ON) at 5V VGS (3.3V VGS if the PVCC input supply is 3.3V) to minimize resistive power loss while they are conducting current. They must also have low gate charge to minimize transition losses during switching. On the other hand, voltage breakdown requirements in a typical LTC1702 circuit are pretty tame: the 7V maximum input voltage limits the VDS and VGS the MOSFETs can see to safe levels for most devices. Low RDS(ON) RDS(ON) calculations are pretty straightforward. RDS(ON) is the resistance from the drain to the source of the MOSFET when the gate is fully on. Many MOSFETs have RDS(ON) specified at 4.5V gate drive--this is the right number to use in LTC1702 circuits running from a 5V supply. As current flows through this resistance while the MOSFET is on, it generates I2R watts of heat, where I is the current flowing (usually equal to the output current) and R is the MOSFET RDS(ON). This heat is only generated when the MOSFET is on. When it is off, the current is zero and the power lost is also zero (and the other MOSFET is busy losing power). This lost power does two things: it subtracts from the power available at the output, costing efficiency, and it makes the MOSFET hotter--both bad things. The effect is worst at maximum load when the current in the MOSFETs and thus the power lost are at a maximum. Lowering RDS(ON) improves heavy load efficiency at the expense of additional gate charge (usually) and more cost (usually). Proper choice of MOSFET RDS(ON) becomes a trade-off between tolerable efficiency loss, power dissipation and cost. Note that while the lost power has a significant effect on system efficiency, it only adds up to a watt or two in a typical LTC1702 circuit, allowing the use of small, surface mount MOSFETs without heat sinks. Gate Charge Gate charge is amount of charge (essentially, the number of electrons) that the LTC1702 needs to put into the gate of an external MOSFET to turn it on. The easiest way to visualize gate charge is to think of it as a capacitance from the gate pin of the MOSFET to SW (for Q1) or to PGND (for Q2). This capacitance is composed of MOSFET channel charge, actual parasitic drain-source capacitance and Millermultiplied gate-drain capacitance, but can be approximated as a single capacitance from gate to source. Regardless of where the charge is going, the fact remains that it all has to come out of VCC to turn the MOSFET gate on, and when the MOSFET is turned back off, that charge all ends up at ground. In the meanwhile, it travels through the LTC1702's gate drivers, heating them up. More power lost! In this case, the power is lost in little bite-sized chunks, one chunk per switch per cycle, with the size of the chunk set by the gate charge of the MOSFET. Every time the MOSFET switches, another chunk is lost. Clearly, the faster the clock runs, the more important gate charge becomes as a loss term. Old-fashioned switchers that ran at 20kHz could pretty much ignore gate charge as a loss term; in the 550kHz LTC1702, gate charge loss can be a significant efficiency penalty. Gate charge loss can be the dominant loss term at medium load currents, especially with large MOSFETs. Gate charge loss is also the primary cause of power dissipation in the LTC1702 itself. TG Charge Pump There's another nuance of MOSFET drive that the LTC1702 needs to get around. The LTC1702 is designed to use N-channel MOSFETs for both Q1 and Q2, primarily because N-channel MOSFETs generally cost less and have lower RDS(ON) than similar P-channel MOSFETs. Turning Q2 on is no big deal since the source of Q2 is attached to PGND; the LTC1702 just switches the BG pin between PGND and VCC. Driving Q1 is another matter. The source of Q1 is connected to SW which rises to VCC when Q1 is on. To keep Q1 on, the LTC1702 must get TG one MOSFET VGS(ON) above VCC. It does this by utilizing a floating driver with the negative lead of the driver attached to SW (the source of Q1) and the VCC lead of the driver coming out
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LTC1702
APPLICATIONS INFORMATION
separately at BOOST. An external 1F capacitor CCP connected between SW and BOOST (Figure 2) supplies power to BOOST when SW is high, and recharges itself through DCP when SW is low. This simple charge pump keeps the TG driver alive even as it swings well above VCC. The value of the bootstrap capacitor CCP needs to be at least 100 times that of the total input capacitance of the topside MOSFET(s). For very large external MOSFETs (or multiple MOSFETs in parallel), CCP may need to be increased over the 1F value. INPUT SUPPLY The BiCMOS process that allows the LTC1702 to include large MOSFET drivers on-chip also limits the maximum input voltage to 7V. This limits the practical maximum input supply to a loosely regulated 5V or 6V rail. The LTC1702 will operate properly with input supplies down to about 3V, so a typical 3.3V supply can also be used if the external MOSFETs are chosen appropriately (see the Power MOSFETs section). At the same time, the input supply needs to supply several amps of current without excessive voltage drop. The input supply must have regulation adequate to prevent sudden load changes from causing the LTC1702 input voltage to dip. In most typical applications where the LTC1702 is generating a secondary low voltage logic supply, all of these input conditions are met by the main system logic supply when fortified with an input bypass capacitor. Input Bypass A typical LTC1702 circuit running from a 5V logic supply might provide 1.6V at 10A at one of its outputs. 5V to 1.6V implies a duty cycle of 32%, which means Q1 is on 32% of each switching cycle. During Q1's on-time, the current drawn from the input equals the load current and during the rest of the cycle, the current drawn from the input is near zero. This 0A to 10A, 32% duty cycle pulse train adds up to 4.7ARMS at the input. At 550kHz, switching cycles last about 1.8s--most system logic supplies have no hope of regulating output current with that kind of speed. A local input bypass capacitor is required to make up the difference and prevent the input supply from dropping drastically when Q1 kicks on. This capacitor is usually chosen for RMS ripple current capability and ESR as well as value. The input bypass capacitor in an LTC1702 circuit is common to both channels. Consider our 10A example case with the other side of the LTC1702 disabled. The input bypass capacitor gets exercised in three ways: its ESR must be low enough to keep the initial drop as Q1 turns on within reason (100mV or so); its RMS current capability must be adequate to withstand the 4.6ARMS ripple current at the input and the capacitance must be large enough to maintain the input voltage until the input supply can make up the difference. Generally, a capacitor that meets the first two parameters will have far more capacitance than is required to keep capacitance-based droop under control. In our example, we need 0.01 ESR to keep the input drop under 100mV with a 10A current step and 4.6ARMS ripple current capacity to avoid overheating the capacitor. These requirements can be met with multiple low ESR tantalum or electrolytic capacitors in parallel, or with a large monolithic ceramic capacitor. The two sides of the LTC1702 run off a single master clock and are wired 180 out of phase with each other to significantly reduce the total capacitance/ESR needed at the input. Assuming 100mV of ripple and 10A output current, we needed an ESR of 0.01 and 4.7A ripple current capability for one side. Now, assume both sides are running simultaneously with identical loading. If the two sides switched in phase, all the loading conditions would double and we'd need enough capacitance for 9.4ARMS and 0.005 ESR. With the two sides out of phase, the input current is 4.8ARMS--barely larger than the single case (Figure 7)! The peak current deltas are still only 10A, requiring the same 0.01 ESR rating. As long as the capacitor we chose for the single side application can support the slightly higher 4.8ARMS current, we can add the second channel without changing the input capacitor at all. As a general rule, an input bypass capacitor capable of supporting the larger output current channel can support both channels running simultaneously (see the 2-Phase Operation section for more details). Tantalum capacitors are a popular choice as input capacitors for LTC1702 applications, but they deserve a special caution here. Generic tantalum capacitors have a destruc-
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LTC1702
APPLICATIONS INFORMATION
32% 10A 68% 0 32% 6.8A 0 -3.2A 10A 68% CURRENT IN CIN, SIDE 1 ONLY ICIN = 4.66ARMS, (1-PHASE, 2 SIDES: ICIN = 9.3ARMS) Q1 CURRENT, SIDE 1 ONLY (FOR 1-PHASE, 2 SIDES: MULTIPLY CURRENT BY 2)
32% 18% 32% 18% Q11 CURRENT Q21 CURRENT BOTH SIDES EQUAL LOAD 2-PHASE OPERATION 32% 18% 32% 18% 3.6A 0 -6.4A CURRENT IN CIN, BOTH SIDES EQUAL LOAD ICIN = 4.8ARMS
1702 F07
0
Figure 7
tive failure mechanism when they are subjected to large RMS currents (like those seen at the input of a LTC1702). At some random time after they are turned on, they can blow up for no apparent reason. The capacitor manufacturers are aware of this and sell special "surge tested" tantalum capacitors specifically designed for use with switching regulators. When choosing a tantalum input capacitor, make sure that it is rated to carry the RMS current that the LTC1702 will draw. If the data sheet doesn't give an RMS current rating, chances are the capacitor isn't surge tested. Don't use it! OUTPUT BYPASS CAPACITOR The output bypass capacitor has quite different requirements from the input capacitor. The ripple current at the output of a buck regulator like the LTC1702 is much lower than at the input, due to the fact that the inductor current is constantly flowing at the output whenever the LTC1702 is operating in continuous mode. The primary concern at the output is capacitor ESR. Fast load current transitions at the output will appear as voltage across the ESR of the output bypass capacitor until the feedback loop in the LTC1702 can change the inductor current to match the new load current value. This ESR step at the output is often the single largest budget item in the load regulation calculation. As an example, our hypothetical 1.6V, 10A switcher with a 0.01 ESR output capacitor would expe-
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rience a 100mV step at the output with a 0 to 10A load step--a 6.3% output change! Usually the solution is to parallel several capacitors at the output. For example, to keep the transient response inside of 3% with the previous design, we'd need an output ESR better than 0.0048. This can be met with three 0.014, 470F tantalum capacitors in parallel. INDUCTOR The inductor in a typical LTC1702 circuit is chosen primarily for value and saturation current. The inductor value sets the ripple current, which is commonly chosen at around 40% of the anticipated full load current. Ripple current is set by:
tON(Q2) (VOUT ) L In our hypothetical 1.6V, 10A example, we'd set the ripple current to 40% of 10A or 4A, and the inductor value would be: IRIPPLE =
tON(Q2) (VOUT ) (1.2s)(1.6V ) = = 0.5H IRIPPLE 4A 1.6V with tON(Q2) = 1 - / 550kHz = 1.2s 5V L=
The inductor must not saturate at the expected peak current. In this case, if the current limit was set to 15A, the inductor should be rated to withstand 15A + 1/2 IRIPPLE, or 17A without saturating. FEEDBACK LOOP/COMPENSATION Type 3 Loops In a typical LTC1702 circuit, the feedback loop consists of the modulator, the external inductor and output capacitor, and the feedback amplifier and its compensation network. All of these components affect loop behavior and need to be accounted for in the loop compensation. The modulator consists of the internal PWM generator, the output MOSFET drivers and the external MOSFETs themselves. From a feedback loop point of view, it looks like a linear voltage transfer function from COMP to SW and has a gain roughly
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LTC1702
APPLICATIONS INFORMATION
equal to the input voltage. It has fairly benign AC behavior at typical loop compensation frequencies with significant phase shift appearing at half the switching frequency. The external inductor/output capacitor combination makes a more significant contribution to loop behavior. These components cause a second order LC roll-off at the output, with the attendant 180 phase shift. This roll-off is what filters the PWM waveform, resulting in the desired DC output voltage, but the phase shift complicates the loop compensation if the gain is still higher than unity at the pole frequency. Eventually (usually well above the LC pole frequency), the reactance of the output capacitor will approach its ESR, and the roll-off due to the capacitor will stop, leaving 6dB/octave and 90 of phase shift. See Appendix A, Figure A3. Note that Figure A4 does not apply. So far, the AC response of the loop is pretty well out of the user's control. The modulator is a fundamental piece of the LTC1702 design, and the external L and C are usually chosen based on the regulation and load current requirements without considering the AC loop response. The feedback amplifier, on the other hand, gives us a handle with which to adjust the AC response. The goal is to have 180 phase shift at DC (so the loop regulates) and something less than 360 phase shift at the point that the loop gain falls to 0dB. The simplest strategy is to set up the feedback amplifier as an inverting integrator, with the 0dB frequency lower than the LC pole (Appendix A, Figure A5). This "type 1" configuration is stable but slow and transient response will be less than exceptional. Also, this circuit configuration cannot count on the MIN and MAX comparators to assist with transient recovery, since they monitor the output at the FB pin which is moving no faster than the integrator pole frequency. Appendix A, Figure A6 shows an improved "type 2" circuit that uses an additional pole-zero pair to temporarily remove 90 of phase shift. This allows the loop to remain stable with 90 more phase shift in the LC section, provided the loop reaches 0dB gain near the center of the phase "bump." Type 2 loops work well in systems where the ESR zero in the LC roll-off happens close to the LC pole, limiting the total phase shift due to the LC. The additional phase compensation in the feedback amplifier allows the 0dB point to be at or above the LC pole frequency, improving loop bandwidth substantially over a simple type 1 loop. It still has limited ability to compensate for LC combinations where low capacitor ESR keeps the phase shift near 180 for an extended frequency range. Many LTC1702 circuits exhibit this behavior--they require type 3 compensation. Type 3 loops (Appendix A, Figure A7) use two poles and two zeros to obtain a 180 phase boost in the middle of the frequency band. A properly designed type 3 circuit can maintain acceptable loop stability even when low output capacitor ESR causes the LC section to approach 180 phase shift well above the initial LC roll-off. As with a type 2 circuit, the loop should cross through 0dB in the middle of the phase bump to maximize phase margin. Because most LTC1702 circuits use low ESR output capacitors, type 3 compensation is usually needed to obtain acceptable phase margin with a high bandwidth feedback loop. Feedback Component Selection Selecting the R and C values for a typical type 3 loop is a nontrivial task. The applications shown in this data sheet show typical values, optimized for the power components shown. They should give acceptable performance with similar power components, but will be way off if even one major power component is changed significantly. The only way to ensure proper dynamic behavior and maximize transient response is to recalculate the values specifically for the circuit in question. Appendix A explains feedback component selection in detail. The 25MHz internal op amp in the LTC1702 can generally close a type 3 loop as high as 50kHz before it runs out of bandwidth. CURRENT LIMIT PROGRAMMING Programming the current limit on the LTC1702 is straightforward. The IMAX pin sets the current limit by setting the maximum allowable voltage drop across Q2 (the bottom MOSFET) before the current limit circuit engages. The voltage across Q2 is set by its on-resistance and the current flowing in the inductor, which is the same as the output current. The LTC1702 current limit circuit inverts the voltage at IMAX before comparing it with the negative voltage across Q2, allowing the current limit to be set with a positive voltage.
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To set the current limit, calculate the expected voltage drop across Q2 at the maximum desired current: load, even with a hot MOSFET that is running quite a bit higher than its RDS(ON) spec. FCB OPERATION/SECONDARY WINDINGS The FCB pin can be used in conjunction with a secondary winding on one side of the LTC1702 to generate a third regulated voltage output. This output can be directly regulated at the FCB pin. In theory, a fourth output could be added, either unregulated or with additional external circuitry at the FCB pin. The extra auxiliary output is taken from a second winding on the core of the inductor on one channel, converting it into a transformer (Figure 8). The auxiliary output voltage is set by the main output voltage and the turns ratio of the extra winding to the primary winding. Load regulation at the auxiliary output will be relatively good as long as the main output is running in continuous mode. As the load on the main channel drops and the LTC1702 switches to discontinuous or Burst Mode operation, the auxiliary output will not be able to maintain regulation, especially if the load at the auxiliary output remains heavy. To avoid this, the auxiliary output voltage can be divided down with a conventional feedback resistor string with the divided auxiliary output voltage fed back to the FCB pin (Figure 8). The FCB pin threshold is trimmed to 800mV with 10mV of hysteresis, allowing fairly precise control of the auxiliary voltage. If the LTC1702 is in discontinuous or Burst Mode operation and the auxiliary output voltage drops, the FCB pin will trip and the LTC1702 will resume continuous operation regardless of the load on the main output. The FCB pin removes the requirement that power
VIN VOUT(AUX) CIN TG LTC1702 FCB BG Q2 RFCB1 Q1
VPROG = (IILIM) RDS(ON) + 100mV
ILIM should be chosen to be quite a bit higher than the expected operating current, to allow for MOSFET RDS(ON) changes with temperature. Setting ILIM to 150% of the maximum normal operating current is usually safe and will adequately protect the power components if they are chosen properly. The 100mV term is an approximate factor that corrects for errors caused by ringing on the switch node (illustrated in Figure 6). This factor will change depending on the layout and the components used, but 100mV is usually a good starting point. VDROP is then programmed at the IMAX pin using the internal 10A pull-up and an external resistor: RILIM = VPROG/10A The resulting value of RILIM should be checked in an actual circuit to ensure that the ILIM circuit kicks in as expected. MOSFET RDS(ON) specs are like horsepower ratings in automobiles, and should be taken with a grain of salt. Circuits that use very low values for RIMAX (< 20k) should be checked carefully, since small changes in RIMAX can cause large ILIM changes when the 100mV correction factor makes up a large percentage of the total VPROG value. If VPROG is set too low, the LTC1702 may fail to start up. Accuracy Trade-Offs The VDS sensing scheme used in the LTC1702 is not particularly accurate, primarily due to uncertainty in the RDS(ON) from MOSFET to MOSFET. A second error term arises from the ringing present at the SW pin, which causes the VDS to look larger than (ILOAD)(RDS(ON)) at the beginning of Q2's on-time. These inaccuracies do not prevent the LTC1702 current limit circuit from protecting itself and the load from damaging overcurrent conditions, but they do prevent the user from setting the current limit to a tight tolerance if more than one copy of the circuit is being built. The 50% factor in the current setting equation above reflects the margin necessary to ensure that the circuit will stay out of current limit at the maximum normal
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1702 F08
Figure 8. Regulating an Auxiliary Output with the FCB Pin
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must be drawn from the inductor primary in order to extract power from the auxiliary windings. With the loop in continuous mode, the auxiliary outputs may be loaded without regard to the primary load. Note that if the LTC1702 is already running in continuous mode and the auxiliary output drops due to excessive loading, no additional action can be taken by the LTC1702 to regulate the auxiliary output. POWER GOOD/FAULT FLAGS The PGOOD pins report the status of the output voltage at their respective outputs. Each is an open-drain output that pulls low until the FB pin rises to (VREF - 5%), indicating that the output voltage has risen to within 5% of the programmed output voltage. Each PGOOD pin can interface directly to standard logic inputs if an appropriate pullup resistor is added, or the two pins can be tied together with a single pull-up to give a "both good" signal. Each PGOOD pin includes an internal 100s delay to prevent glitches at the output from indicating false PGOOD signals. The FAULT pin is an additional open-drain output that indicates if one or both of the outputs has exceeded 15% of its programmed output voltage. FAULT includes an internal 10A pull-up to VCC and does not require an external pull-up to interface to standard logic. FAULT pulls low in normal operation, and releases when a overvoltage fault is detected. When an overvoltage fault occurs, an internal latch sets and FAULT goes high, disabling the LTC1702 until the latch is cleared by recycling the power or pulling both RUN/SS pins low simultaneously. Alternately, the FAULT pin can be pulled back low externally with an opencollector/open-drain device or an NFET or NPN, which will allow the LTC1702 to resume normal operation, but will not reset the latch. If the pull-down is later removed, the LTC1702 will latch off again unless the latch is reset by cycling the power or RUN/SS pins. Note that both the PGOOD pins and the FAULT pin monitor the output voltages by watching the FB pins. During normal operation, each FB pin is held at a virtual ground by the feedback amplifier, and changes at the output will not appear at FB. This is not an issue with a properly designed circuit, since the virtual ground at FB implies that the output voltage is under control. If the feedback amplifier loses control of the output, the virtual ground disappears and the PGOOD circuit can see any output changes. This occurs whenever the soft start or current limit circuits are active, whenever the MIN or MAX comparators are active, or any time the feedback amplifier output (the COMP pin) hits a rail or is in slew limit. Since the MAX comparator will engage well before the output reaches the +15% fault level, the FAULT output is largely unaffected by the virtual ground at FB. OPTIMIZING PERFORMANCE 2-Step Conversion The LTC1702 is ideally suited for use in 2-step conversion systems. 2-step systems use a primary regulator to convert the input power source (batteries or AC line voltage) to an intermediate supply voltage, often 5V. The LTC1702 then converts the intermediate voltage to the low voltage, high current supplies required by the system. Compared to a 1-step converter that converts a high input voltage directly to a very low output voltage, the 2-step converter exhibits superior transient response, smaller component size and equivalent efficiency. Thermal management and layout complexity are also improved with a 2-step approach. A typical notebook computer supply might use a 4-cell Li-Ion battery pack as an input supply with a 15V nominal terminal voltage. The logic circuits require 5V/3A and 3.3V/5A to power system board logic, and 2.5V/0.5A, 1.8V/2A and 1.5V/10A to power the CPU. A typical 2-step conversion system would use a step-down switcher (perhaps an LTC1628 or two LTC1625s) to convert 15V to 5V and another to convert 15V to 3.3V (Figure 9). One channel of the LTC1702 would generate the 1.5V supply using the 3.3V supply as the input and the other channel would generate 1.8V using the 5V supply as the input. The corresponding 1-step system would use four similar stepdown switchers, each using 15V as the input supply and generating one of the four output voltages. Since the 2.5V supply represents a small fraction of the total output power, either system can generate it from the 3.3V output using an LDO linear regulator, without the 75% linear
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VBAT 15V 5V/3A LTC1628* LTC1702 1.8V/2A 1.5V/10A 3.3V/5A *OR TWO LTC1625s LDO 2.5V/0.5A
1702 F09
Figure 9. 2-Step Conversion Block Diagram
efficiency making much of an impact on total system efficiency. Clearly, the 5V and 3.3V sections of the two schemes are equivalent. The 2-step system draws additional power from the 5V and 3.3V outputs, but the regulation techniques and trade-offs at these outputs are similar. The difference lies in the way the 1.8V and 1.5V supplies are generated. For example, the 2-step system converts 3.3V to 1.5V with a 45% duty cycle. During the Q1 on-time, the voltage across the inductor is 1.8V and during the Q2 on-time, the voltage is 1.5V, giving roughly symmetrical transient response to positive and negative load steps. The 1.8V maximum voltage across the inductor allows the use of a small 0.47H inductor while keeping ripple current under 4A (40% of the 10A maximum load). By contrast, the 1-step converter is converting 15V to 1.5V, requiring just a 10% duty cycle. Inductor voltages are now 13.5V when Q1 is on and 1.5V when Q2 is on, giving vastly different di/dt values and correspondingly skewed transient response with positive and negative current steps. The narrow 10% duty cycle usually requires a lower switching frequency, which in turn requires a higher value inductor and larger output capacitor. Parasitic losses due to the large voltage swing at the source of Q1 cost efficiency, eliminating any advantage the 1-step conversion might have had. Note that power dissipation in the LTC1702 portion of a 2-step circuit is lower than it would be in a typical 1-step converter, even in cases where the 1-step converter has higher total efficiency than the 2-step system. In a typical microprocessor core supply regulator, for example, the regulator is usually located right next to the CPU. In a 1-step design, all of the power dissipated by the core
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regulator is right there next to the hot CPU, aggravating thermal management. In a 2-step LTC1702 design, a significant percentage of the power lost in the core regulation system happens in the 5V or 3.3V supply, which is usually away from the CPU. The power lost to heat in the LTC1702 section of the system is relatively low, minimizing the heat near the CPU. 2-Step Efficiency Calculation Calculating the efficiency of a 2-step converter system involves some subtleties. Simply multiplying the efficiency of the primary 5V or 3.3V supply by the efficiency of the 1.8V or 1.5V supply underestimates the actual efficiency, since a significant fraction of the total power is drawn from the 3.3V and 5V rails in a typical system. The correct way to calculate system efficiency is to calculate the power lost in each stage of the converter, and divide the total output power from all outputs by the sum of the output power plus the power lost: Efficiency = Total Output Power 100% Total Output Power + Total Power Lost
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In our example 2-step system, the total output power is: Total output power = 15W + 16.5W + 1.25W + 3.6W + 15W = 51.35W corresponding to 5V, 3.3V, 2.5V, 1.8V and 1.5V output voltages. Assuming the LTC1702 provides 90% efficiency at each output, the additional load on the 5V and 3.3V supplies is: 1.5V: 15W/90% = 16.6W/3.3V = 5A from 3.3V 1.8V: 3.6W/90% = 4W/5V = 0.8A from 5V 2.5V: 1.25W/75% = 1.66W/3.3V = 0.5A from 3.3V If the 5V and 3.3V supplies are each 94% efficient, the power lost in each supply is: 1.5V: 1.8V: 2.5V: 3.3V: 5V: 16.6W - 15W = 1.6W 4W - 3.6W = 0.4W 1.66W - 1.25W = 0.4W 17.55W - 16.5W = 1W 16W - 15W = 1W
Total loss = 4.4W
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APPLICATIONS INFORMATION
Total system efficiency = 51.35W/(51.35W + 4.4W) = 92.1%
EFFICIENCY (%)
Maximizing High Load Current Efficiency Efficiency at high load currents (when the LTC1702 is operating in continuous mode) is primarily controlled by the resistance of the components in the power path (Q1, Q2, LEXT) and power lost in the gate drive circuits due to MOSFET gate charge. Maximizing efficiency in this region of operation is as simple as minimizing these terms. The behavior of the load over time affects the efficiency strategy. Parasitic resistances in the MOSFETs and the inductor set the maximum output current the circuit can supply without burning up. A typical efficiency curve (Figure 10) shows that peak efficiency occurs near 30% of this maximum current. If the load current will vary around the efficiency peak and will spend relatively little time at the maximum load, choosing components so that the average load is at the efficiency peak is a good idea. This puts the maximum load well beyond the efficiency peak, but usually gives the greatest system efficiency over time, which translates to the longest run time in a battery-powered system. If the load is expected to be relatively constant at the maximum level, the components should be chosen so that this load lands at the peak efficiency point, well below the maximum possible output of the converter. Maximizing Low Load Current Efficiency Low load current efficiency depends strongly on proper operation in discontinuous and Burst Mode operations. In an ideally optimized system, discontinuous mode reduces conduction losses but not switching losses, since each power MOSFET still switches on and off once per cycle. In a typical system, there is additional loss in discontinuous mode due to a small amount of residual current left in the inductor when Q2 turns off. This current gets dissipated across the body diode of either Q1 or Q2. Some LTC1702 systems lose as much to body diode conduction as they save in MOSFET conduction. The real efficiency benefit of discontinuous mode happens when Burst Mode operation is invoked. At typical power levels, when Burst Mode operation is activated, gate drive is the dominant loss term. Burst Mode operation turns off all output switching for several clock cycles in a row, significantly cutting gate
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1 LOAD CURRENT (A)
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1702 F10
Figure 10. Typical LTC1702 Efficiency Curve for 10A Circuit
drive losses. As the load current in Burst Mode operation falls toward zero, the current drawn by the circuit falls to the LTC1702's background quiescent level--about 3mA per channel. To maximize low load efficiency, make sure the LTC1702 is allowed to enter discontinuous and Burst Mode operation as cleanly as possible. FCB must be above its 0.8V threshold. Minimize ringing at the SW node so that the discontinuous comparator leaves as little residual current in the inductor as possible when Q2 turns off. It helps to connect the SW pin of the LTC1702 as close to the drain of Q2 as possible. An RC snubber network can also be added from SW to PGND. See the Layout/Troubleshooting section for more layout advice. REGULATION OVER COMPONENT TOLERANCE/ TEMPERATURE DC Regulation Accuracy The LTC1702 initial DC output accuracy depends mainly on internal reference accuracy, op amp offset and external resistor accuracy. Two LTC1702 specs come into play: feedback voltage and feedback voltage line regulation. The feedback voltage spec is 800mV 8mV over the full temperature range, and is specified at the FB pin, which encompasses both reference accuracy and any op amp offset. This accounts for 1% error at the output with a 5V input supply. The feedback voltage line regulation spec adds an additional 0.05%/V term that accounts for change in reference output with change in input supply voltage.
LTC1702
APPLICATIONS INFORMATION
With a 5V supply, the errors contributed by the LTC1702 itself add up to no more than 1% DC error at the output. The output voltage setting resistors (R1 and RB in Figure 3) are the other major contributor to DC error. At a typical 1.xV output voltage, the resistors are of roughly the same value, which tends to halve their error terms, improving accuracy. Still, using 1% resistors for R1 and RB will add 1% to the total output error budget, equal to that of all errors due to the LTC1702 combined. Using 0.1% resistors in just those two positions can nearly halve the DC output error for very little additional cost. Load Regulation Load regulation is affected by feedback voltage, feedback amplifier gain and external ground drops in the feedback path. Feedback voltage is covered above and is within 1% over temperature. A full-range load step might require a 10% duty cycle change to keep the output constant, requiring the COMP pin to move about 100mV. With amplifier gain at 85dB, this adds up to only a 10V shift at FB, negligible compared to the reference accuracy terms. External ground drops aren't so negligible. The LTC1702 can sense the positive end of the output voltage by attaching the feedback resistor directly at the load, but it cannot do the same with the ground lead. Just 0.001 of resistance in the ground lead at 10A load will cause a 10mV error in the output voltage--as much as all the other DC errors put together. Proper layout becomes essential to achieving optimum load regulation from the LTC1702. See the Layout/Troubleshooting section for more information. A properly laid out LTC1702 circuit should move less than a millivolt at the output from zero to full load. TRANSIENT RESPONSE Transient response is the other half of the regulation equation. The LTC1702 can keep the DC output voltage constant to within 1% when averaged over hundreds of cycles. Over just a few cycles, however, the external components conspire to limit the speed that the output can move. Consider our typical 5V to 1.6V circuit, subjected to a 1A to 5A load transient. Initially, the loop is in regulation and the DC current in the output capacitor is zero. Suddenly, an extra 4A start flowing out of the output capacitor while the inductor is still supplying only 1A. This sudden change will generate a (4A)(CESR)voltage step at the output; with a typical 0.015 output capacitor ESR, this is a 60mV step at the output, or 3.8% (for a 1.6V output voltage). Very quickly, the feedback loop will realize that something has changed and will move at the bandwidth allowed by the external compensation network towards a new duty cycle. If the bandwidth is set to 50kHz, the COMP pin will get to 60% of the way to 90% duty cycle in 3s. Now the inductor is seeing 3.4V across itself for a large portion of the cycle, and its current will increase from 1A at a rate set by di/dt = V/L. If the inductor value is 0.5H, the di/dt will be 3.4V/0.5H or 6.8A/s. Sometime in the next few microseconds after the switch cycle begins, the inductor current will have risen to the 5A level of the load current and the output voltage will stop dropping. At this point, the inductor current will rise somewhat above the level of the output current to replenish the charge lost from the output capacitor during the load transient. During the next couple of cycles, the MIN comparator may trip on and off, preventing the output from falling below its - 5% threshold until the time constant of the compensation loop runs out and the main feedback amplifier regains control. With a properly compensated loop, the entire recovery time will be inside of 10s. Most loads care only about the maximum deviation from ideal, which occurs somewhere in the first two cycles after the load step hits. During this time, the output capacitor does all the work until the inductor and control loop regain control. The initial drop (or rise if the load steps down) is entirely controlled by the ESR of the capacitor and amounts to most of the total voltage drop. To minimize this drop, reduce the ESR as much as possible by choosing low ESR capacitors and/or paralleling multiple capacitors at the output. The capacitance value accounts for the rest of the voltage drop until the inductor current rises. With most output capacitors, several devices paralleled to get the ESR down will have so much capacitance that this drop term is negligible. Ceramic capacitors are an exception; a small ceramic capacitor can have suitably low ESR with relatively small values of capacitance, making this second drop term significant.
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Optimizing Loop Compensation Loop compensation has a fundamental impact on transient recovery time, the time it takes the LTC1702 to recover after the output voltage has dropped due to output capacitor ESR. Optimizing loop compensation entails maintaining the highest possible loop bandwidth while ensuring loop stability. Appendix A describes in detail the techniques used to design an optimized type 3 feedback loop, appropriate for most LTC1702 systems. Measurement Techniques Measuring transient response presents a challenge in two respects: obtaining an accurate measurement and generating a suitable transient to use to test the circuit. Output measurements should be taken with a scope probe directly across the output capacitor. Proper high frequency probing techniques should be used. In particular, don't use the 6" ground lead that comes with the probe! Use an adapter that fits on the tip of the probe and has a short ground clip to ensure that inductance in the ground path doesn't cause a bigger spike than the transient signal being measured. Conveniently, the typical probe tip ground clip is spaced just right to span the leads of a typical output capacitor. Make sure the bandwidth limit on the scope is turned off, since a significant portion of the transient energy occurs above the 20MHz cutoff. Now that we know how to measure the signal, we need to have something to measure. The ideal situation is to use the actual load for the test, and switch it on and off while watching the output. If this isn't convenient, a current step generator is needed. This generator needs to be able to turn on and off in nanoseconds to simulate a typical switching logic load, so stray inductance and long clip leads between the LTC1702 and the transient generator must be minimized. Figure 11 shows an example of a simple transient generator. Be sure to use a noninductive resistor as the load element--many power resistors use an inductive spiral pattern and are not suitable for use here. A simple solution is to take ten 1/4W film resistors and wire them in parallel to get the desired value. This gives a noninductive resistive load which can dissipate 2.5W continuously or 50W if pulsed with a 5% duty cycle, enough for most LTC1702
LTC1702 RLOAD PULSE GENERATOR 0V TO 10V 100Hz, 5% DUTY CYCLE IRFZ44 OR EQUIVALENT 50 LOCATE CLOSE TO THE OUTPUT VOUT
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Figure 11. Transient Load Generator
circuits. Solder the MOSFET and the resistor(s) as close to the output of the LTC1702 circuit as possible and set up the signal generator to pulse at a 100Hz rate with a 5% duty cycle. This pulses the LTC1702 with 500s transients 10ms apart, adequate for viewing the entire transient recovery time for both positive and negative transitions while keeping the load resistor cool. FAULT BEHAVIOR Changing the Output Voltage on the Fly Some applications use a switching scheme attached to the feedback resistors to allow the system to adjust the LTC1702 output voltage. The voltage can be changed on the fly if desired, but care must be taken to avoid tripping the overvoltage fault circuit. Stepping the voltage upwards abruptly is safe, but stepping down quickly by more than 15% can leave the system in a state where the output voltage is still at the old higher level, but the feedback node is set to expect a new, substantially lower voltage. If this condition persists for more than 10s, the overvoltage fault circuitry will fire and latch off the LTC1702. The simplest solution is to disable the fault circuit by grounding the FAULT pin. Systems that must keep the fault circuit active should ensure that the output voltage is never programmed to step down by more than 15% in any single step. The safest strategy is to step the output down by 10% or less at a time and wait for the output to settle to the new value before taking subsequent steps. VID Applications Certain microprocessors specify a set of codes that correspond to power supply voltages required from the regulator system. If these codes are changed on the fly, the same
LTC1702
APPLICATIONS INFORMATION
caveats as above apply. In addition, the switching matrix that programs the output voltage may vary its resistance significantly over the entire span of output voltages, potentially changing the loop compensation if the circuit is not designed properly. With a typical type 3 feedback loop (Appendix A, Figure A7), make sure that the RBIAS resistor is modified to set the output voltage. The R1 resistor must stay constant to ensure that the loop compensation is not affected.
APPE DIX A
THE K FACTOR: A NEW MATHEMATICAL TOOL FOR STABILITY ANALYSIS AND SYNTHESIS H. Dean Venable, President Venable Industries, Inc. 2120 W. Braker Lane, Suite M Austin, TX 78758 info@venableind.com http://www.venableind.com Abstract
Analysis of the stability of feedback loops has always been a subject that was shrouded in mystery and confusion. Recent efforts to clear away some of these problems have helped, but even with computer-aided design, a certain amount of trial-and-error remained. This paper presents a new mathematical concept that is simple but powerful. The techniques described allow synthesis of a feedback amplifier with a few algebraic equations to obtain any desired crossover frequency and phase margin (within reason) on the first try. 1. INTRODUCTION Stability analysis of feedback loops has historically required a certain amount of trial-and-error. Computer modeling and computer-aided design allowed one to evaluate results of a particular design with relative ease, but it was still difficult to start with a designed result and then determine the exact circuit values required to obtain that result. This paper presents three standardized feedback amplifiers which cover the requirements for every known loop. These amplifiers, together with a new mathematical concept called the K Factor, allow the circuit designer to choose a desired result, i.e., a particular loop cross-over frequency and phase margin, and then determine the necessary component values to achieve these results from a few straight-forward algebraic equations. Venable Industries, Inc. specializes in the sale and support of computer-controlled Frequency Response Analyzer test systems designed for the power supply industry. Written in 1983, the K Factor paper is a mathematical convention that led us to our current product capabilities. Today, Venable's software instantly designs all of the compensation values for this circuit topology and others, automatically calculating values based on test or model data. This feature saves valuable design time. It enables engineers to quickly and accurately measure the frequency response of components and analog circuits as well as test impedance across the frequency domain. Most importantly, the Venable Frequency Response Analyzer system allows engineers to optimally stabilize feedback loops.
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APPE DIX A
2. THE NATURE OF LOOPS A typical loop is shown in Figure A1. The loop consists of a power-processing block called a MODULATOR in series with an error-detecting block called an AMPLIFIER. The modulator can be as simple as the buck regulator shown, or it could have been a complex hydraulic servo system or an aircraft attitude control system. No matter how complicated the modulator, the principle is the same: a portion of the output is compared to a reference in an error amplifier, and the difference is amplified and inverted and used as a control input for the modulator to keep the controlled variable constant. Even in multiple-loop systems, there is still one main loop that performs this function. 3. WHAT STABILITY MEANS 3.1 The Nature of Stability There is no problem with a control loop at DC. It is obvious that negative feedback tends to make the controlled output more constant. The problem comes at some higher frequency. Reactive components and time delays cause phase shifts which tend to increase the phase shift around the loop. There is a 180 degree phase shift at DC. At some frequency, the additional phase shift from reactive components and time delays is equal to 180 degrees also, so that an error signal at this frequency will be shifted a total of 360 degrees as it progresses around the loop, and comes back in phase with the original signal. If the net of all the amplitude gains and losses around the loop is one or greater at this frequency, then the error signal is selfperpetuating and the circuit becomes an oscillator. The object of stability analysis is to find a way to keep the total phase shift from reaching 360 degrees before the loop gain falls below unity (0 dB). This is shown graphically in Figure A2. The difference between the actual total phase shift and 360 degrees when the gain is unity is called PHASE MARGIN. The amount the gain is below unity when the total phase shift reaches 360 degrees is called GAIN MARGIN. 3.2 The Importance of Phase It is possible to stabilize a loop just by reducing the gain of the amplifier until loop cross-over occurs at a frequency well below that where phase shifts from reactive components start to become significant. The problem with this approach is that the response time of the loop to a transient disturbance is slowed down to the point where it is usually unacceptable. In any high-performance loop, the object is to cross over at as high a frequency as possible, while maintaining good phase margin. This is
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Figure A1. Closed Loop Circuit
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Figure A2. Stability Criteria
LTC1702
APPE DIX A
accomplished by tailoring the frequency response of the error amplifier to compensate for some of the modulator phase shift in the region of gain cross-over. A principle objective of this paper is to examine the nature of this "tailoring," and to derive equations that allow loop performance to be predicted without iterative "trial-and-error" procedures. 4. THE NATURE OF MODULATORS The modulator, or power-processing portion of a circuit, can take many forms. Because of the general nature of modulators, each one has to be analyzed individually. In switching power supplies, however, the transfer function of the modulator usually takes one of two forms: either buck-derived or boost-derived. 4.1 Buck-Derived Modulators Figure A3 shows a typical transfer function of a buckderived modulator. An electrical transfer function of a circuit is the output voltage divided by the input voltage, with both the magnitude and phase angle of this ratio plotted as a function of frequency. In buck-derived switching regulators with L-C filters, the transfer function usually has some fixed value, AV, at low frequency, associated with minimal phase shift. At the resonance of the L-C filter, the transfer function breaks to a - 2 slope (a -1 slope falls 20 dB/decade, a - 2 slope falls 40 dB/decade, etc.). A - 2 slope is associated with - 180 degrees of phase shift. At some frequency (usually, but not always, higher than the frequency of the L-C corner) the internal resistance of the filter capacitor (ESR) becomes higher than the capacitive reactance, and the slope of the transfer function curve changes to - 1 as the filter changes from an L-C filter to an L-R filter. The phase shift associated with a -1 slope is - 90 degrees, provided the response is determined by real components. 4.2 Boost-Derived Modulators Figure A4 shows the transfer function of a boost-derived modulator. The gain portion of a boost-derived modulator looks very much like the gain portion of a buck-derived modulator. There are some major differences in the gain portion, however, and the phase portion is obviously different. Most boost-derived modulators also have a region of fixed gain at low frequency, again associated with a minimal phase shift; however the value of gain in this region is usually a non-linear function of operating point. There is a point in frequency where the transfer function breaks to a - 2 slope, as in the buck-derived case, but this frequency is also a function of operating point because the effective value of inductance changes with duty cycle. The phase shift associated with the - 2 slope region is the same in either case, - 180 degrees. The major problem in boost-derived modulators is caused by a right-
GAIN (dB) GAIN -2
AV
0
Figure A3. Transfer Function of Buck Modulator
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PHASE (DEG)
GAIN (dB) GAIN -2 0
PHASE (DEG)
AV
0
0
PHASE
PHASE -90
-90
-180
-180 -1
-1 -270
1702 APP F03
1702 APP F04
Figure A4. Transfer Function of Boost Modulator
27
LTC1702
APPE DIX A
half plane zero, a mathematical entity that nevertheless causes real problems. The frequency at which the righthalf plane zero occurs is related to the effective value of the filter inductance and the load resistance, and usually occurs at a low enough frequency (typically several kilohertz) that the effect of it must be considered when trying to optimize loop performance. A right-half plane zero causes the gain curve to break from a - 2 to a - 1 slope, the same as a left-half plane zero, but the phase shifts 90 degrees negative instead of positive. No practical amplifier offers enough phase boost to compensate for this phenomenon, so modulators with boost-derived transfer functions are restricted to cross-over frequencies below the frequency of the right-half plane zero. Recently, Dr. Fred Lee and others have proposed techniques generally referred to as "multiple-loop feedback" methods, wherein a signal from the energy storage inductor is fed into the pulse width modulator circuit to change the basic transfer function of the modulator, eliminating the right-half plane zero, and even reducing the - 2 slope portion of the modulator to a - 1 slope by using current feedback. These modifications are very helpful in obtaining good performance from boost-derived modulators by changing the basic nature of their transfer functions, but do not change the basic techniques described herein for stabilizing loops. No matter what type of modulator is used, or what modifications are incorporated to change the modulator transfer function, the techniques for stabilization of the loop are exactly the same. One of the three basic amplifiers described below will still suffice to stabilize any loop. 5. THE THREE BASIC AMPLIFIERS 5.1 Fundamental Assumptions In all cases, it is assumed that a real op-amp is used and that the system is configured so that negative feedback (inversion) is required in the amplifier. It is possible to stabilize loops using the internal error amplifier provided in most PWM chips, but it is difficult to optimize performance since the transfer function is generally based on internal component values which are poorly specified and therefore unpredictable. It is also possible, although difficult, to stabilize loops using an error amplifier in the noninverting mode. The trouble with this mode is that the gain is restricted to values greater than one, and this is not always compatible with the desired transfer function of the amplifier. For best performance, the internal amplifier of the PWM chip should be wired as an inverting or noninverting buffer, whichever allows the external error amplifier to be inverting. For the SG1524 family of chips, for example, the internal amplifier should be wired as a non-inverting buffer for positive output voltages and as an inverting buffer for negative output voltages. For the TL494 family of chips, which have the opposite internal sense, the internal amplifier should be wired as an inverting buffer for positive output voltages, and as a noninverting buffer for negative output voltages. 5.2 Type 1 Amplifier Figure A5 shows a Type 1 amplifier and its transfer function. The Type 1 amplifier has a single pole at the origin and the gain rolls off at a - 1 slope forever, crossing unity gain at the frequency where the reactance of C1 is equal in magnitude to the resistance of R1. This type of amplifier has - 270 degrees of phase shift throughout the - 1 slope region, and is used to compensate loops where the phase shift of the modulator is minimal, for example, below the L-C filter corner. 5.3 Type 2 Amplifier Figure A6 shows a Type 2 amplifier and its transfer function. The Type 2 amplifier also has a pole at the origin, but has a zero-pole pair in addition. This zero-pole pair causes a region of zero gain slope and a corresponding phase "bump", or region of reduced phase shift. Whereas the phase shift is - 270 degrees throughout the -1 slope regions of the amplifier transfer function, in the zero slope region the phase shift tends toward - 180 degrees. The amount of phase shift reduction (size of the "bump") is related to the width of the zero slope region and has a maximum value of 90 degrees. The frequency at which the zero occurs is approximately that where R2 takes out C1, that is, where the reactance of C1 is equal in magnitude to the resistance of R2. The frequency at which the pole
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LTC1702
APPE DIX A
C2
C1
Figure A5a. Type 1 Amplifier Schematic Diagram Figure A6a. Type 2 Amplifier Schematic Diagram
GAIN (dB) GAIN PHASE (DEG)
0 -1
Figure A5b. Type 1 Amplifier Transfer Function
occurs is approximately that where C2 takes out R2, that is, where the reactance of C2 is equal in magnitude to the resistance of R2. Type 2 amplifiers are used to compensate loops where the phase shift of the modulator portion is approximately - 90 degrees. The transfer function of the amplifier is designed so that overall loop cross-over occurs in the center of the zero gain slope region. The zeropole pair is frequently referred to as a "lead" network. Notice that the output of an amplifier can never lead the input, and that a "lead" network can be more accurately described as a "reduction in lag" network. 5.4 Type 3 Amplifier Figure A7 shows a Type 3 amplifier and its transfer function. A Type 3 amplifier also has a pole at the origin, but in addition has two zero-pole pair. The two zeros are coincident and the two poles are coincident, resulting in a region of +1 gain slope and a corresponding phase "bump",
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R2
R1 IN RBIAS VREF - + OUT
C1
R1 IN RBIAS
- + VREF OUT
1702 APP F05a
1702 APP F06a
GAIN (dB) -1 GAIN 0 -1 0
PHASE (DEG)
0
0
-90
-90
-180
PHASE
-180
PHASE -270
1702 APP F05b
-270
1702 APP F06b
Figure A6b. Type 2 Amplifier Transfer Function
or region of reduced phase shift. Whereas the phase shift is - 270 degrees throughout the - 1 slope regions of the amplifier transfer function, in the +1 slope region the phase shift tends toward - 90 degrees. The amount of phase shift reduction (size of the "bump") is related to the width of the +1 slope region, and has a maximum value of 180 degrees. The frequency where the two zeros occur is approximately where R2 takes out C1 and C3 takes out R1, and the frequency where the two poles occur is approximately where C2 takes out R2 and R3 takes out C3, where "takes out" means the capacitive reactance is equal in magnitude to the resistance. Type 3 amplifiers are used to compensate loops where the phase shift of the modulator portion is approximately -180 degrees at the frequency of desired loop gain cross-over. The transfer function of the amplifier is designed so that overall loop cross-over occurs in the center of the +1 slope region. Type 3 amplifiers have the most phase boost of any practical
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LTC1702
APPE DIX A
C2 C3 R3 R2 R1 IN RBIAS VREF C1
Figure A7a. Type 3 Amplifier Schematic Diagram
GAIN (dB) -1 GAIN 0 +1 -1
Figure A7b. Type 3 Amplifier Transfer Function
amplifier configuration. It is not practical to compensate for more than 180 degrees of phase lag in the modulator portion. If the phase shift of the modulator at the chosen cross-over frequency is greater than 180 degrees, steps should be taken to cross the loop over at a lower frequency (frequency with less phase lag), or modify the modulator circuit to reduce the amount of phase lag at the desired cross-over frequency. 6. THE K FACTOR 6.1 Introduction to the K Factor The K Factor was originally conceived of as an aid in the synthesis of amplifiers. It is defined as the square root of the ratio of the pole frequency to the zero frequency for Type 2 amplifiers, or the ratio of the double pole frequency
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- + OUT
1702 APP F07a
PHASE (DEG)
0
-90
-180 PHASE -270
1702 APP F07b
to the double zero frequency for Type 3 amplifiers. Figure A8 shows the relationship between the loop cross-over frequency, f, and location of the zeros and poles of the amplifier transfer function. Type 1 amplifiers always have a K of 1. A Type 2 amplifier has a zero at f/K and a pole at Kf, therefore f is the geometric mean of the zero frequency and the pole frequency. The peak phase boost from the zero-pole pair occurs at frequency f, and it is assumed that the amplifier is designed so that overall loop cross-over occurs at frequency f also. For a Type 3 amplifier, the frequency of the double zero is f divided by the square root of K and the frequency of the double pole is f times the square root of K. Frequency f is then the geometric mean between the frequency of the double zero and the frequency of the double pole. The peak of the phase boost from the two zero-pole pair occurs at frequency f, and it assumed that the amplifier is designed such that the overall loop cross-over occurs at frequency f also. In each case, the larger the K, the larger the phase boost. 6.2 Tradeoffs of K Factor Value There is a penalty associated with using zero-pole pair to increase phase margin that is evident from looking at Figure A8. No matter what type of amplifier is chosen, the K factor is a direct measure of the reduced gain at low frequency and increased gain at high frequency which result from the zero-pole pair, both undesirable side effects of the quest for more phase margin. The K factor can then be thought of the gain penalty that is paid for increased phase margin. 6.3 f/K as a Figure of Merit To improve overall loop performance, one's first thought is to increase the loop cross-over frequency. If this increase happens to coincide with a frequency range where the modulator phase lag is increasing rapidly, K may have to be increased faster than f to maintain the same phase margin, in which case the low frequency gain will actually suffer from the increased cross-over frequency. The expression f/K can therefore be thought of as a Figure of Merit for a particular amount of phase margin.
LTC1702
APPE DIX A
LOG GAIN K=1 -1
LOG GAIN
LOG GAIN
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G 1 G 1
G 1
7. DERIVATION OF THE K FACTOR The Type 1 amplifier always has a K of 1, so deriving the K factor for it is not a problem. Also, the mathematics for determining the amount of boost from given locations of amplifier zeros and poles is well understood. The problem that had not been solved was to derive equations that expressed the location of the zeros and poles as a function of phase boost. 7.1 Derivation of K for Type 2 Amplifiers The expression for the amount of phase boost from a zeropole pair is well known and has been presented before. The phase shift due to a zero or pole is given by the inverse tangent of ratio of the measurement frequency to the frequency at which the zero or pole is located. The principle of superposition applies, that is, the total amount of phase shift can be determined by summing the individual phase shifts of each zero and pole taken individually. The boost at frequency f from a zero at frequency f/K and a pole at frequency Kf is given by the equation: Boost = Tan-1(K) - Tan-1(1/K) From the trigonometric identity, Tan-1(X) + Tan-1(1/X) = 90 degrees (1) (2)
f
LOG FREQ
1702 APP F08a
Figure A8a. Type 1 Amplifier
TYPE 1 REF K
f K
f
Kf K
LOG FREQ
1702 APP F08b
Figure A8b. Type 2 Amplifier
the amount of boost can be determined by substituting (2) in (1): Boost = Tan-1(K) + Tan-1(K) - 90 = 2 Tan-1(K) - 90 (3)
K
TYPE 1 REF
From equation (3),
LOG FREQ K
f K
f
fK
Tan-1(K)= (Boost + 90)/2 = (Boost/2) + 45 Therefore: K = Tan[(Boost/2) + 45]
(4) (5)
1702 APP F08c
Figure A8c. Type 3 Amplifier
Equation (5) is the equation that relates the K factor to the amount of phase boost required from Type 2 amplifiers to achieve the desired phase margin. From this, the exact location of the zeros and poles is established, and the loop
31
LTC1702
APPE DIX A
cross-over frequency and phase margin may be calculated without trial-and-error. 7.2 Derivation K for Type 3 Amplifiers Type 3 amplifiers have a double zero at a frequency f divided by the square root of K and a double pole at a frequency f times the square root of K. The phase boost from a single zero-pole pair at these frequencies is given by the equation: Boost = Tan-1K - Tan-1(1/K) (6) For 2 zero-pole pairs, where the zeros are coincident and the poles are coincident, there is twice the boost that results from only 1 zero-pole pair, therefore the boost that results from a Type 3 amplifier is: Boost = 2[Tan-1K - Tan-1(1/K)] (7) Incorporating the trigonometric identity given in (2) into (7), Boost = 2(Tan-1K + Tan-1K - 90) = 2[2(Tan-1K) - 90] = 4(Tan-1K) - 180 Equation (8) can now be rearranged to solve for K: Tan-1K = (Boost + 180)/4 = (Boost/4) + 45 K = Tan [(Boost/4) + 45 K = {Tan[(Boost/4) + 45]}2 (9) (10) (11) (8) 8.1.1 Make Bode Plots of the Modulator This can be done by analysis or measurement, but preferably by measurement since it is difficult by analysis alone to include all the parasitic effects. Instruments to perform this measurement are called Frequency Response Analyzers. A number of companies manufacture this type of equipment. For switching regulators and similar applications where there is a significant amount of electrical noise present along with the signal, Fourier Integral Analysis machines are far superior to Fast Fourier Transform machines. Venable Industries offers several different complete Frequency Response Analysis Systems, all based on Fourier Integral Analysis machines. 8.1.2 Choose a Cross-over Frequency The second step in the process is to choose the frequency at which you would like the overall loop gain to be unity. This is f, the cross-over frequency. This is normally chosen to be as high as possible, since higher cross-over frequency normally means faster transient response, and "as high as possible" means where the modulator phase shift is still less than 180 degrees. If the circuit has to be built in volume, where there may be significant differences in component values from unit to unit, or if it will be subjected to wide extremes of line, load, and temperature, it is best not to push the loop to extremes. 8.1.3 Choose the Desired Phase Margin Pick the amount of phase margin you would like to have at unity gain. A phase margin of 90 degrees means your system is stable as a rock. Phase margin of 60 degrees is a good compromise between fast transient response and stability. Phase margins of 30 degrees or less cause the system to have substantial ringing when subjected to transients, and little tolerance for component or environmental variations. 8.1.4 Determine Required Amplifier Gain The fourth step is to determine the required amplifier gain at cross-over. The amplifier gain at cross-over must equal the modulator loss, therefore the amplifier gain = 1/modulator gain. If the gain is expressed in dB, then the amplifier gain is simply the negative of the modulator gain.
Equation (11) is the final equation expressing the K factor as a function of desired phase boost for a Type 3 amplifier. The location of the double zero and double pole is then established. 8. USING THE K FACTOR 8.1 Preliminary Steps When using the K factor to synthesize an amplifier to stabilize a feedback loop, certain preliminary steps apply regardless of the type of amplifier chosen. These steps are as follows:
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LTC1702
APPE DIX A
8.1.5 Calculate Required Phase Boost Calculate the amount of phase boost required from the zero-pole pair in the amplifier from the formula: Boost = M - P - 90 where M = Desired Phase Margin (degrees) and P = Modulator Phase Shift (degrees) 8.1.6 Choose an Amplifier Type Once the amount of boost required is determined, you can choose what type of amplifier to use. Type 1 amplifier. The Type 1 amplifier is used where no boost is required. This is the case where a loop is crossed over before the frequency of the L-C corner, for example. This is the simplest type of amplifier and requires the fewest parts. Type 2 amplifier. The Type 2 amplifier is used where the required boost is less than 90 degrees, and is most practical when the required boost is less than about 70 degrees, since a very large K factor is required as the boost approaches 90 degrees. It is used for loops where the modulator gain curve is falling off at about a -1 slope, and the phase shift is about - 90 degrees. This is the case in current regulators, or in voltage regulators above the frequency of the ESR zero of the main filter capacitor. Type 3 amplifier. The Type 3 amplifier is used where the required phase boost is less than 180 degrees. It offers the most boost for a given K factor of any of the amplifier types, but has the highest parts count also. A loop with a Type 3 amplifier will always perform better than one with a Type 1 or Type 2, where "better" is defined as more low frequency gain and less high frequency gain for a given cross-over frequency and amount of phase margin. 8.1.7 Choose a Value for R1 The final preliminary step is to choose a value for R1, the input resistor to the amplifier. This is normally based on how much current you want to draw from the modulator output. If the modulator is a low power, high voltage supply, R1 would typically be very large. If the modulator is a high power, low voltage supply, R1 can usually be selected arbitrarily. The current through R1 should be (12) much larger than the input and bias currents of the operational amplifier used as an error amplifier. Care should be taken not to make the value of R1 too small, however, since all of the other compensation components scale in direct proportion to R1, and a low value for R1 means large values for the compensation capacitors. Large compensation capacitors, in addition to costing more, require more current to drive as a network, and may overload the output of the operational amplifier. A bias resistor, RBIAS, is connected from the inverting input of the error amplifier to ground. This resistor is used to set the DC operating point of the loop, but has no effect on the ac operation, and does not enter into the calculations for cross-over frequency and phase margin. 8.2 Subsequent Steps After the seven initial steps, the subsequent steps vary, depending on which type of amplifier you chose. In each case, the following notes and definitions apply: (1) Resistors are in ohms, capacitors are in farads, phase is in degrees, frequency is in hertz, gain is a dimensionless ratio (not dB), and K is a dimensionless ratio. (2) f = chosen cross-over frequency (3) G = Amplifier gain at cross-over (4) K = K factor (5) R and C values refer to components in the three basic amplifier schematics shown in Figures 5, 6, and 7. 8.2.1 Subsequent Steps - Type 1 The following equations apply to Type 1 amplifiers only: K=1 C1 = 1/(2 f G R1) (13) (14)
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A Type 1 amplifier is somewhat different from the others, in that there is no phase boost. For this reason, the phase margin of the overall loop with a Type 1 amplifier is 90 degrees, less whatever phase lag the modulator has at the chosen cross-over frequency. 8.2.2 Subsequent Steps - Type 2 The following equations apply to Type 2 amplifiers only:
33
LTC1702
APPE DIX A
K = Tan[(Boost/2) + 45] C2 = 1/(2 f G K R1) C1 = C2 (K2 -1) R2 = K /(2 f C1) (15) (16) (17) (18) proper gain at a particular frequency. There is nothing that can be done to optimize a Type 2 amplifier either, although this may not be so obvious. With the K factor, the gain as well as the location of the zero and pole are determined for a particular operating point, and there is nothing you can do about the performance at other operating points other than live with what you get. It is the Type 3 amplifier that is intriguing, since the K factor assumptions are that the zeros and poles are coincident. What if the zeros and poles are not coincident? What if the zeros or poles or both are spread apart somewhat? Look at Figure 8c. For the same K factor, that is, the same penalty in low frequency gain, spreading the zeros or poles means flattening the sharp corners, moving one zero or pole toward cross-over frequency f, and the other zero or pole away. The net effect of this is to broaden and flatten the phase "bump", so that the phase margin at cross-over is reduced. Optimum performance, that is, the most phase margin for the smallest K factor, is obtained when the zeros and poles are coincident. It may be the case, however, that a particular circuit may have wide excursions of line, load, and temperature, which lead to wide variations in the modulator transfer function. In special cases such as this, it may be advantageous to sacrifice optimum performance at a particular point, in order to gain satisfactory performance over a wide operating range. 9. SUMMARY Three basic amplifiers were developed which can be used to stabilize any known feedback loop. A new mathematical tool, the K Factor, was developed, and a set of design equations were presented based on the K factor. These design equations allow the precise determination of loop performance without the iterative process normally associated with stability analysis. These techniques have been extensively tested at Venable Industries, and allow even a relatively unskilled person to stabilize a loop with remarkable accuracy and speed.
This completes the synthesis of the Type 2 feedback amplifier. With these component values, the overall loop gain will be unity at frequency f, and the phase margin will be as specified, provided the required boost was between 0 and 90 degrees. It is worthwhile to verify that required amplifier gain at all frequencies is less than the open loop gain of the amplifier, since op amps are not truly ideal devices. Reactance-frequency graph paper is an excellent medium to use for this, since the verification can be done in a few moments and the results provide a better "feel" for the design. 8.2.3 Subsequent Steps - Type 3 The following equations apply to Type 3 amplifiers only: K = {Tan[(Boost/4) + 45]}2 C2 = 1/(2 f G R1) C1 = C2(K - 1) R2 = K /(2 f C1) R3 = R1/(K - 1) C3 = 1/(2 f K R3) (19) (20) (21) (22) (23) (24)
This completes the synthesis of a Type 3 feedback amplifier. With these component values, the overall loop gain will be unity at frequency f, and the phase margin will be as specified, provided the required boost is between 0 and 180 degrees. It is worthwhile to verify that the required amplifier gain at all frequencies is less than the open loop gain of the amplifier, since op amps are not truly ideal devices. As with the Type 2 amplifier, reactance-frequency graph paper is an excellent medium to use for this. 8.3 Optimization It is obvious that there is nothing that can be done to optimize a Type 1 amplifier, other than to choose the
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LTC1702
APPE DIX A
REFERENCES (1) Venable, H. Dean, "Practical Techniques for Analyzing, Measuring, and Stabilizing Feedback Control Loops in Switching Regulators and Converters", Proceedings of the Seventh National Power Conversion Conference, POWERCON 7, pp. I2-1 to I2-17, March, 1980. (2) Venable, H. Dean, "Stability Analysis Made Simple", Rancho Palos Verdes, CA, Venable Industries, 1982. (3) Middlebrook, R. D., and Cuk, Slobodan, "Advances in Switched-Mode Power Conversion, Volume I", Pasadena, CA TESLAco, 1981. (4) Cuk, Slobodan, and Middlebrook, R. D., "Advances in Switched-Mode Power Conversion, Volume II", Pasadena, CA, TESLAco, 1981. (5) Lee, F. C., and Yu, Y., "Application Handbook for a Standardized Control Module for DC-DC Converters", NASA Report Volume I and II, NAS3-20102, 1980.
PACKAGE DESCRIPTION
0.015 0.004 x 45 (0.38 0.10) 0.007 - 0.0098 (0.178 - 0.249) 0.016 - 0.050 (0.406 - 1.270) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP
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dimensions in inched (millimeters) unless otherwise anoted.
GN Package 24-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.337 - 0.344* (8.560 - 8.738) 24 23 22 21 20 19 18 17 16 15 1413
0.033 (0.838) REF
0.229 - 0.244 (5.817 - 6.198)
0.150 - 0.157** (3.810 - 3.988)
1
23
4
56
7
8
9 10 11 12
0.053 - 0.068 (1.351 - 1.727)
0.004 - 0.0098 (0.102 - 0.249)
0.008 - 0.012 (0.203 - 0.305)
0.025 (0.635) BSC
GN24 (SSOP) 0398
35
LTC1702
TYPICAL APPLICATION
Single Output, 2-Phase, 5V to 1.5V/20A Converter
VIN 5V
0.1F
7 5 6 2 10k
LT1218 3 4
10k 0.1F
4.7k
560pF VCC PVCC BOOST1
6.98k 8.06k 0.1% 0.1% 4.7k 560pF
FB1 330pF 680pF COMP1 13k RUN/SS1 0.1F RUN/SS2 FB2 680pF COMP2 13k IMAX1 18k IMAX2
6.8k 10k
330pF 8.2k
PGOOD2 GND FAULT FCB PGND
*KEMET T510X477M006AS Q1 TO Q6: FAIRCHILD FDS6670A L1, L2: MURATA LQT12535C1ROM12
RELATED PARTS
PART NUMBER LTC1530 LTC1625 LTC1628 LTC1735 LTC1735-1 LTC1736 DESCRIPTION High Power Synchronous Step-Down Controller No RSENSE Current Mode Synchronous Step-Down Controller 2-Phase, Dual Synchronous Step-Down Controller Synchronous Step-Down Controller Synchronous Step-Down Controller with Power Good Synchronous Step-Down Controller with 5-Bit VID Control COMMENTS SO-8 with Current Limit. No RSENSE Required No Sense Resistor Required, VIN = 3.7V to 36V; VOUT = 1.19V to VIN Reduces Capacitors, Extends Battery Life, OPTI-LOOPTM, VIN = 3.5V to 36V VOUT = 0.8V to 6V; 99% Duty Cyle 1%, 0.8V Reference Lowest Cost Dynamic VID Solution for Pentium(R)III Processor Output Fault Protection, Powergood
OPTI-LOOP is a trademark of Linear Technology Corporation. Pentium is a registered trademark of Intel Corp.
36
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
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10
0.003 0.5W 0.003 0.5W
- +
+
470F*
+ +
10F
+
470F*
470F* MBR0530T MBR 0530T
1F TG1 SW1 BG1 TG2 SW2 BG2 PGOOD1 PGOOD FAULT 1 1 Q5 Q6 1F Q4 1 1 Q3 Q1
L1 1H, 12A
Q2
LTC1702 BOOST2
MBR 330T
+
L2 1H, 12A
VOUT 1.5V 20A 470F* x2
MBR 330T
1702 TA02
1702i LT/TP 0599 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1999

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